Data Bus Size of SDRAM for MPC855T

[takahidenakayam]

Equipment with MPC855T CPU has been developed, but we're going to eliminate 1 of SDRAM for production cost reduction and change the data bus width of an external memory to 16bit from 32bit.FEC is being used, but does change in the data bus width influence DMA movement of FEC?

[takahidenakayam]

Thank you very much for your comment.

We discuss an application notebook.

[r8070z]

Have a great day,

Yes decreasing of the data bus width will influence to DMA movement of FEC and will increase the risk of the FEC FIFO underrun. You can estimate that in way suggested in application note 860T Design Advisory

http://cache.nxp.com/files/netcomm/doc/app_note/AN2064.pdf

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