Hi,
I was hoping someone can verify/clarify some passages from the datasheet (Rev. 7).
Passage
12.3: When DFS enabled, the FS state machine monitors and counts faults happening.
Question
- If DFS is disabled, does the FS state machine not monitor and count faults happening? FLT_ERR_CNT never increments?
- In that case, is it correct to assume that the intermediate value impact will never trigger?
Passage
12.5.3: The fault error counter is incremented by 1, each time RSTB and/or FS0B pin is asserted. When FS0B is asserted, the fault error counter is incremented by 1, every time the watchdog error counter maximum value is reached.
Question
- If RSTB and/or FS0B is asserted through SPI request, does it still count towards FLT_ERR_CNT, or only when RSTB/FS0B is asserted as part of a fault impact?
- If a fault occurs (e.g. VCORE undervoltage) but is configured to have no impact on FS0B or RSTB (e.g. VCORE is not safety critical) am I correct to assume it will not increment FLT_ERR_CNT? E.g. the selected impact on safety outputs FS0B and RSTB determines if it will increment the fault counter?
- Same question but regarding specifically the second half of the passage: If FS0B is not asserted when the watchdog error counter maximum value is reached, it doesn't increment FLT_ERR_CNT? SO also for the watchdog, the impact defines FLT_ERR_CNT behaviour?
Passage
12.7.1.6 and 12.7.2.4: The overvoltage detection switches off the regulator.
Question
Regarding the disabling of the regulator; is it permanently switched off, until the next Wake-up or POR?
I hope I have understood these passages correctly, but I would like to verify.
Kind regards,
Joey