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PF3000/3001 + IMX6UL/6ULL reference design
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Hi      VVDN Technologies is NXP Partner, more information and technology support about I.MX reference design , you can find in the link below:     NXP - Partner Profile Information     About I.MX6ULL and I.MX6UL with PF1550 reference design, you can find the schematic in attachment. BRs 
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Hi,  Other than stating it's Automotive Qualified, does the 2 parts have any difference? Or they are still equivalent? ie.  MPN 1: 74HC4060PW-Q100,11 MPN 2: 74HC4060PW,118 Thank you!
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Introduction The BMA7118 and BMA7418 belong to NXP's latest family of 18-channel Li-ion battery cell controller ICs for advanced battery management systems. These devices are designed to provide accurate cell monitoring, low current consumption, integrated balancing, functional safety support, and scalable communication, making them suitable for demanding automotive and industrial battery applications. For customers interested in electrochemical impedance spectroscopy, the BMA7418 includes dedicated EIS support, while the BMA7118 provides a strong baseline solution with a convenient upgrade path within the same family. 1) What are BMA7118 and BMA7418? The BMA7118 and BMA7418 are NXP battery cell controller ICs designed for monitoring and balancing lithium-ion cells in battery management systems. They support 8 to 18 cells per device and are intended for applications such as EVs, HEVs, and industrial energy storage systems. 2) What is the main difference between BMA7118 and BMA7418? The main difference is EIS support. The BMA7418 includes integrated Discrete Fourier Transform functionality to support electrochemical impedance spectroscopy, while the BMA7118 targets high-accuracy battery monitoring without EIS. Both devices belong to the same product family and are positioned as pin- and software-compatible. 3) How many cells can one device monitor? One device can monitor from 8 up to 18 cells. This gives designers flexibility to optimize the battery architecture and reduce the number of monitoring ICs needed in larger battery packs. 4) What applications are these devices intended for? Typical target applications include automotive battery management systems for electric and hybrid vehicles, as well as industrial battery systems such as stationary energy storage and related electrification platforms. 5) What level of cell-voltage accuracy can I expect? The family is designed for very high measurement accuracy with ultra-low long-term drift. Typical accuracy for the family is ±0.8 mV, supporting precise battery monitoring and improved system performance. 6) Why is “dedicated ADC per voltage channel” important? Using a dedicated ADC for each voltage channel helps avoid the timing limitations of multiplexed measurement approaches. This supports highly synchronized cell measurements, which can improve SOC and SOH calculations and is especially important for EIS-capable systems. 7) What communication options are available? Depending on the variant, communication with the host MCU can be implemented through SPI or through an isolated daisy-chain transport protocol link (TPL). The daisy-chain approach supports scalable high-voltage battery systems with multiple monitoring nodes. 😎 How does the family support functional safety? The family is designed to support ASIL D-oriented battery management architectures. It includes redundant measurement paths, diagnostic functions, fault reporting, and safety-related monitoring features intended to support robust system-level functional safety designs. 9) Can the device measure temperatures and auxiliary signals? Yes. In addition to cell voltages, the devices support auxiliary analog inputs (AINx) that can be used for temperature sensing through external NTC networks and for other auxiliary measurements. These pins can also be configured as GPIOs. 10) What are the power-consumption advantages of this family? A key benefit is the integrated DC-DC converter, which helps reduce overall power consumption compared to solutions that rely on less efficient supply approaches. This can be beneficial for both active operation and low-power battery system scenarios. 11) What balancing capability is integrated? The family integrates passive balancing control with internal balancing FETs and supports balancing across up to 18 cells. It includes features such as timer-based balancing, voltage-based balancing, PWM-based balancing control, and protection-oriented timeout behavior. 12) Can balancing continue in low-power modes? Yes. Balancing support in low-power operating states is one of the useful capabilities of the family. This helps enable battery maintenance functions such as parked-vehicle balancing while still keeping power consumption low. 13) Does balancing influence measurement accuracy? Balancing can influence measured voltage values because current flow through external paths may create small voltage drops. To address this, the device supports balancing pause concepts so that measurements can be taken under more stable conditions when required. 14) Which operating modes are available? Multiple operation modes, including Deep Sleep, Sleep, Active, and Cyclic mode. These allow the system designer to balance measurement performance, wake-up behavior, and current consumption according to the use case. Deep Sleep is the lowest-current startup/storage state with almost no state retention. Sleep keeps key configuration and can allow balancing. Active enables full functionality. In Cyclic mode the device runs measurements in the configured intervals, and moves back to sleep or enters active mode afterward depending on the measurement results. 15) How are overvoltage and undervoltage conditions handled? The devices support configurable threshold checking for measured channels. When configured limits are exceeded, status information can be updated and event mechanisms can be used to notify the host controller or trigger an appropriate system response. 16) What development hardware and software are available? We offer evaluation boards for the BMA7x18 family (EVBMA7118DT, EVBMA7X18DT1), together with software tools (EvalGUI, BMS GEN2 SDK) and broader battery management ecosystem support. 17) Which orderable variants are available? The family includes SPI and TPL variants for both BMA7118 and BMA7418. This allows customers to choose the communication architecture that best matches their battery management system topology. 18) What is BMI7018, and how does it relate to BMA7118/BMA7418? The BMI7018 is an 18-channel Li-ion battery cell controller IC for industrial applications, especially energy storage systems (ESS) and uninterruptible power supplies (UPS). It is not the same product family as BMA7118/BMA7418, but it is highly relevant for customers looking for an NXP battery cell controller optimized for industrial use cases rather than automotive ASIL-D battery packs. It is s tailored to industrial mission profiles, and is characterized for industrial conditions rather than automotive AEC-Q100 Grade 1 positioning. 19) Does BMI7018 support EIS like BMA7418? No. BMI7018 is not positioned as an EIS-capable device. Customers specifically looking for electrochemical impedance spectroscopy support should use BMA7418 instead.  
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Introduction The TEA2376 is a digital configurable two-phase interleaved PFC controller intended for high-efficiency power supplies. It supports DCM / QR operation with valley switching, programmable protections, phase shedding, burst mode, and MTP-based parameter configuration. The TEA2376DT variant additionally supports dedicated I²C pins for live parameter access during operation, a POWERGOOD output, and a BURST input, making it especially suitable for development and system interaction. 1) What is the TEA2376? The TEA2376 is a digital configurable interleaved PFC controller with two phases for high-efficiency power supplies. It is intended for applications such as TVs, servers, PCs, gaming consoles, high-power adapters, 5G supplies, home audio, and similar products that require high power factor, low THD, and good efficiency over a wide load range. 2) What is the difference between the TEA2376AT, TEA2376BT, and TEA2376DT? The main differences are package and I²C / system-interface capabilities. TEA2376AT is offered in an SO10 package and uses the GATE1/GATE2 pins for I²C communication during programming. TEA2376BT is offered in an SO14 package but still uses combined GATE pins for I²C and does not add POWERGOOD or BURST system pins. TEA2376DT is also in an SO14 package, but it provides a POWERGOOD output, a BURST input, and dedicated SDA/SCL pins for live I²C communication during operation, which makes it the most convenient variant for development work. 3) What are the main benefits of an interleaved PFC compared to a single-phase PFC? An interleaved PFC divides the power over two out-of-phase boost channels. This reduces stress per phase, distributes losses and heat, reduces RMS ripple current in the output capacitor, and improves EMI behavior because part of the ripple current cancels in the input path. It can also reduce cooling requirements and make high-power designs easier to realize. 4) What operating modes does the TEA2376 support? The TEA2376 supports normal two-phase operation for medium and high load, phase shedding at light load, and burst mode at very low load. The controller mainly operates in discontinuous conduction mode or quasi-resonant mode with valley switching, while brief CCM operation may occur under special conditions such as start-up when the input voltage is close to the output voltage. 5) What power level is the TEA2376 intended for? The TEA2376 family is intended for power levels up to typically 1000 W. The actual achievable power depends on the complete system design, including switching frequency, thermal performance, magnetics, MOSFETs, PCB layout, and cooling conditions. 6) What protections are included in the TEA2376? The TEA2376 includes a broad set of protections, such as VCC undervoltage and overvoltage protection, internal and external overtemperature protection, inrush current protection, brownin / brownout, overcurrent protection on SNSCUR and SNSSRC, dual output overvoltage protection, coil short protection, output diode short protection, open / short pin protection, open-loop protection, and phase-fail protection. Many of these protections can be configured independently for latched behavior or safe restart. 7) How is the TEA2376 programmed? The TEA2376 uses I²C programming for loading and modifying settings during development. For AT and BT versions, I²C communication shares the GATE1/GATE2 pins, so the IC must be placed into the correct start-up state to enable programming. For the DT version, I²C is available on dedicated SDA/SCL pins, which allows programming and monitoring while the application is operating. 😎 Can I modify parameters while the power supply is running? Yes, but only with the TEA2376DT. Its dedicated SDA/SCL pins support live I²C communication during operation. AT and BT versions are less convenient for live tuning because I²C is multiplexed on the gate pins and the application must be placed into the appropriate programming state. 9) What is the TEA2376DK1011 kit? The TEA2376DK1011 is a programming and development kit that includes TEA2376DT IC samples and a TEA2376DB1604v3 programming board. The board provides sockets for both SO10 and SO14 devices and routes the I²C connections correctly for supported TEA2376 variants. The kit is intended to help users get started quickly with evaluation, programming, and parameter tuning. 10) What additional hardware and software do I need to use the TEA2376DK1011? The programming setup requires a Windows PC, the TEA2376 Ringo software, an I²C-USB interface with cables (RDK01DB1563), and the TEA2376DB1604 programming board. The Ringo software requires the appropriate USB-I²C interface driver to be installed. 11) What does the TEA2376DB1604 programming board actually do? The TEA2376DB1604 is an IC connection and programming board. It routes the I²C signals to the correct pins, supplies VCC to the IC, provides sockets for both SO10 and SO14 packages, includes protection on the I²C connection, and offers test points for observing the communication signals. A switch allows VCC to be connected or disconnected during IC exchange. 12) What is the TEA2376DB1602v2 demo board and what does it demonstrate? The TEA2376DB1602v2 is a 300 W interleaved PFC demo board that combines the TEA2376DT interleaved PFC controller with the TEA2209T active bridge rectifier controller. It operates from a universal AC mains input of 90 V(RMS) to 264 V(RMS) and is intended to demonstrate and evaluate a single-output PFC power stage with programmable settings, interleaving, phase shedding, burst mode, and active bridge rectification. It is also positioned as a starting point for developing power supplies based on the TEA2376 and TEA2209 controller ICs. 13) What key performance can users expect from the TEA2376DB1602v2 board? In the documented reference configuration, the board regulates to a nominal output voltage of 395 V and is specified for up to 300 W continuous output power. The start-up time is about 100 ms at 115 V/60 Hz and full load. Efficiency is greater than 96% at 115 V/60 Hz and greater than 98% at 230 V/50 Hz, with measured averages of 97.2% and 98.2%, respectively. The no-load input power is 25 mW at 115 V/60 Hz and 30 mW at 230 V/50 Hz, while the power factor at full load is 0.99. 14) What are the typical operating-mode transitions and thermal limits of the TEA2376DB1602v2 board? The demo board uses three operating modes: normal mode, phase shedding, and burst mode. At 230 V mains, the transition points are approximately 39 W from burst mode to phase shedding, 86 W from phase shedding to normal mode, 50 W from normal mode back to phase shedding, and 23 W from phase shedding back to burst mode. At 115 V mains, the corresponding transition points are approximately 39 W, 99 W, 59 W, and 29 W. Thermally, the board was designed without heat sinks and remains within acceptable component temperatures at 300 W in laboratory conditions, with a measured maximum temperature of 82 °C at 115 V mains and 300 W, and 100 °C at 100 V mains and 300 W. Higher power levels are possible, but fan cooling is required to avoid overheating. 15) What are phase shedding and burst mode, and why do they matter? Phase shedding disables one PFC phase at light load so that the remaining phase can operate more efficiently. Burst mode periodically stops switching at very low load to reduce controller and conversion losses. Together, these mechanisms help improve light-load and standby efficiency and support compliance with modern efficiency requirements. 16) How can burst mode be controlled? Burst mode can be configured in several ways depending on the device version and MTP settings. It can be controlled via the VCC pin, via the SNSBOOST pin, and on the TEA2376DT also via the dedicated BURST input pin. Supported burst operation styles include follow mode, ripple mode, and autonomous mode. 17) What are POWERGOOD and BURST pins used for on the TEA2376DT? These are DT-only system-interface features. POWERGOOD is an open-drain output that indicates that the PFC output is above a programmable minimum level and that the controller is operating normally, depending on the selected settings. BURST is an input that allows an external system or downstream converter to command burst-mode behavior, with programmable polarity and thresholds. 18) Can the TEA2376 work together with TEA2209 and TEA19161? Yes. The TEA2376 is often being used together with the TEA2209 active bridge rectifier controller and the TEA19161 LLC controller in high-efficiency AC/DC power systems. The TEA19161 can also interact with TEA2376 through SNSBOOST-based burst-mode coordination during low-load operation. 19) What performance does NXP demonstrate with TEA2376 in the 1 kW standalone design example? In the TEA2376DB1623 1 kW standalone PFC design example, the performance measurements report a 385 V output, power factor greater than 0.99 over the tested mains range at full load, THD below 10 percent in the reported tests, and efficiency above 98 percent at 1 kW depending on mains condition. These values are for the specific demo-board implementation and test conditions. 20) What are typical mode-transition points in the 1 kW example? For the TEA2376DB1623 1 kW design example, the reported transition levels are approximately 312 to 317 W for phase adding, 209 to 213 W for phase shedding, 115 to 117 W for entering burst mode, and 148 to 149 W for leaving burst mode. These are example settings from that design and can be changed through MTP configuration. 21) Is the TEA2376DK1011 or demo hardware intended for end-product use? No. The kit and demo boards are intended for engineering development and evaluation purposes only. They are open-frame boards intended for laboratory use by qualified personnel and are not intended for production use. 22) Is there anything important to know about AT/BT programming through GATE pins? Yes. For AT and BT versions, I²C communication shares the gate pins, so the IC must be placed into the correct programming state by appropriate handling during start-up. In practical terms, this makes AT and BT less convenient than DT for repeated live tuning during development. 23) Why is the TEA2376DT usually the preferred version for development? TEA2376DT combines dedicated SDA/SCL pins, live I²C communication during operation, a POWERGOOD output, a BURST input, and GUI-based status monitoring. These features make it the most flexible variant for tuning, debugging, and system integration work.
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MC3377XC CB function measurement by GUI   Many customers need test MC33771/2 cell balancing function, this article will introduce this function test detail step by step by setting in NXP MC3377X GUI.   Below simple diagram shows the internal cell balancing switches arrangement example for MC33772C. During test also refer to these switches positions to measurement the voltage variation on balancing resistors.                               Figure1 For below picture is MC33772C GUI setting,the cell balancing feature is active in Normal, Sleep and Diagnostic modes.   The SYS_CFG1 register contains the CB_DRVEN bit. The CB_DRVEN bit must be enabled for any of the drivers to be activated. All drivers are disabled when CB_DRVEN bit is logic 0.   For cell balance drivers to be active, both the SYS_CFG1[CB_DRVEN] and the CBx_CFG[CB_EN] bits must be set to logic 1.   The individual cell balance timer is set through the CBx_CFG[CB_TIMER]. Timing parameters can be found in the register map of this specification. Each time the cell balance CBx_CFG[CB_TIMER] bit is written by the MCU controller, the MC33772C initiates the cell balance timer.   It is important to explicitly mention, each time the CB_DRVEN bit is set to logic 0, then cell balancing timers get reset to 0 (the CBx_CFG[CB_TIMER] bits are unchanged) and all cell balancing MOSFETs are turned off.   Before the CB_DRVEN bit is set again to logic 1, all CBx_CFG registers need to be configured again.   Otherwise, a cell balancing sequence will be started with the previous settings. The SYS_CFG1 register contains the CB_MANUAL_PAUSE bit, which, if set to logic 1, instructs the MC33772C to disable the cell balance switches.   When the CB_MANUAL_PAUSE bit is set again to logic 0, the cell balance switches are restored according to the programming.   However, the cell balance timers are not frozen during a manual pause. The contents of CBx_CFG[CB_TIMER] and ADC2_OFFSET_COMP[ALLCBOFF_ON_SHORT] bits must not be changed while balancing.                                  Figure2   Below are the cell balancing funciton test steps:   1:Customer can select EVB of KIT33772CTPLEVB and 6 cells or BATT-6EMULATOR,according user manual UM11562 to set up this test platform.  KIT33772CTPLEVB: TPL evaluation board for MC33772C | NXP Semiconductors BATT-6EMULATOR | Battery Emulator for MC33772 | NXP Semiconductors   2:According Figure1 balancing resistors positions to match them in the EVB for expediently measurement. You can also download KIT33772CTPLEVB schematic from below link: KIT33772CTPLEVB Schematics                                   Figure3 Match the Figure1 balancing resistors with about Figure3 green circled parts.   3:Figure2 is the operation on GUI, after correctly connection MC33772 EVB and battery you can accord above explain of CB function to verify or setting related registers.   4:Enable CBDrvEn bit before test this CB function.   For example when testing SW1 ON in the Figure1, it is necessary to enable the CBEN/STS bit of CB_CFG_1, and then test the voltage change of TP235, which will change from 0 to the voltage value of Cell1.   If you use the BATT-6EMULATOR you can slide battery1 channel to change its value for verify this operation.   In the default value the CBDrvEn bit and CBEN/STS bits are OFF.     5:Also in Figure1 when testing SW2 ON, enable the CBEN/STS bits of CB_CFG_1 and CB_CFG_2 simultaneously.   You will find that the value of TP234 will change from the voltage value of Cell1+Cell2 to the value of Cell1.   6:It is also possible to test that the voltage across R1 will change from 0V to the voltage value of Cell2, when only the enable CBEN/STS bit of CB_CFG_2 and also SW2 is enabled.   7: And so on. The subsequent tests will continue until the end   In the test will use the GUI which can be downloaded from below link:  : https://www.nxp.com/design/design-center/development-boards-and-designs/FRDM33772BSPIEVB  
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Introduce this OVP function and simulation: Over Voltage Protection Circuit Introduction and Simulation
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Please see attached documentation for FS26XX OTP instruction. Thanks!
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Please see attached file.  
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This attached file introduce PF5300 AVP function and simulation result.  
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For more detail please see attached file.
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This is NXP PMIC solution for Non-NXP Processor.  Link: https://www.nxp.com/products/power-management/pmics-and-sbcs/pmics-and-sbcs-for-multi-vendor-processors:PMICS-SBCS-MULTI-VENDOR-PROCESSORS No AN Title PMIC Processor Application Link 1 AN12883 Multiple low voltage PMIC system Low voltage PMIC NA NA https://www.nxp.com/webapp/Download?colCode=AN12883&appType=moderatedWithoutFAE 2 AN12807 Complete system power solution using FS84/FS85 and PF502x family FS85,PF502x NA NA https://www.nxp.com/webapp/Download?colCode=AN12807&appType=moderatedWithoutFAE 3 AN4991 Power Management of Xilinx AP SoC Using Freescale PMIC PF0100 Xilinx Zynq-7000  Industrial,consumer https://www.nxp.com/docs/en/application-note/AN4991.pdf 4 AN13002 NXP PMIC solution for Mobileye EyeQ4 mid processor PF5024+PF5020 Mobileye EyeQ4 ADAS https://www.nxp.com.cn/docs/en/application-note/AN13002.pdf 5 AN13020 NXP PMIC solution for RH850 series MCU FS65,FS23,FS26,FS85 Renesas RH850 Electrification, Cluster,body, General purpose, https://www.nxp.com.cn/docs/en/application-note/AN13020.pdf 6 AN13018 NXP PMIC solution for R-Car M3 Processor PF81*2 Renesas RcarM3 IVI https://www.nxp.com.cn/docs/en/application-note/AN13018.pdf 7 AN13019 NXP PMIC solution for Renesas R-Car E3 Processor PF71 Renesas RcarE3 Cluster https://www.nxp.com.cn/docs/en/application-note/AN13019.pdf 8 AN13003 NXP PMIC solution for Renesas R-Car H3 processor PF82+PF5020+PF5024+PF52 Renesas RcarH3 IVI,ADAS https://www.nxp.com.cn/docs/en/application-note/AN13003.pdf 9 AN13058 NXP PMIC solution for Renesas R-Car V3M processor PF5024+PF5020 Renesas RcarV3M ADAS https://www.nxp.com.cn/docs/en/application-note/AN13058.pdf 10 AN13197 NXP PMIC solution for Toshiba TMPV7608 processor PF71 Toshiba TMPV7608 ADAS https://www.nxp.com.cn/docs/en/application-note/AN13197.pdf 11 AN13239 NXP PMIC solution for ESPRESSIF ESP32 PF1550 ESPRESSIF ESP32 NON-AUTO https://www.nxp.com.cn/docs/en/application-note/AN13239.pdf 12 AN13245 NXP PMIC solution for TI C2000 FS45,FS85 TI C2000 Electrification https://www.nxp.com.cn/docs/en/application-note/AN13245.pdf 13 AN13246 NXP PMIC solution ST Chorus ST58 FS65,FS85 ST Chorus ST58 Electrification https://www.nxp.com.cn/docs/en/application-note/AN13246.pdf 14 AN13247 NXP PMIC solution for MTK processor 2712 FS56+PF81+PF5024 MTK 2712 IVI https://www.nxp.com/docs/en/application-note/AN13247.pdf 15 AN13272 NXP PMIC solution for Ambarella CV22/CV25 SoC FS56+PF81 FS85+PF82 Ambaralla CV22/CV25  ADAS https://www.nxp.com.cn/docs/en/application-note/AN13272.pdf  16 AN13320 NXP PMIC solution for XILINX UltraScale+ MPSoC ZU2/ZU3 Processor FS56+PF81 FS85+PF71+PF5020+PF5024 Xilinx Zynq UltraScale+ MPSoC ZU2/ZU3 ADAS https://www.nxp.com.cn/docs/en/application-note/AN13320.pdf 17 AN13318 NXP PMIC solution for Ambarella Horizon J2 FS56+PF81 FS85+PF82 Horizon J2 ADAS https://www.nxp.com.cn/docs/en/application-note/AN13318.pdf 18 AN13222 NXP SBC solution for Infineon AURIX TC2xx/TC3xx series MCU FS26 FS45/FS65 FS85 Infineon AURIX TC2xx/TC3xx Electrification,ADAS https://www.nxp.com.cn/docs/en/application-note/AN13322.pdf 19 AN13431 NXP PMIC solution for TI TMS570 MCU FS26,FS45,FS65,FS85 TI TMS570 MCU Electrification,powertrain https://www.nxp.com.cn/docs/en/application-note/AN13431.pdf 20 AN13432 NXP PMIC solution for XILINX UltraScale+ MPSoC ZU4\ZU5\ZU6\ZU7\ZU9 Processor FS56,FS86,PF81,PF71,PF5020,PF52 XILINX UltraScale+ MPSoC ZU4\ZU5\ZU6\ZU7\ZU9  ADAS https://www.nxp.com.cn/docs/en/application-note/AN13432.pdf 21 AN13433 NXP PMIC solution for XILINX UltraScale+ MPSoC ZU11_ZU15 Processor PF7100,PF5023,PF5200,FS86 XILINX UltraScale+ MPSoC ZU11_ZU15 ADAS https://www.nxp.com.cn/docs/en/application-note/AN13433.pdf 22 AN13554 NXP PMIC solution for SAMA5Dx series processor PF1550,PF1510 Microchip SAMA5DX NON-AUTO https://www.nxp.com.cn/docs/en/application-note/AN13554.pdf 23 AN13615 NXP PMIC solution for AG55xQ series module FS56 AG55xQ V2X https://www.nxp.com.cn/docs/en/application-note/AN13615.pdf 24 AN13638 NXP PMIC Solution for TI TDA2x_TDA2Ex Processor FS56+PF81 TI TDA2 ADAS https://www.nxp.com/docs/en/application-note/AN13638.pdf 25 AN13651 PMIC solution for TI AWR2243 radar transceiver FS56+PF71/PF5020 TI AWR2243 Radar https://www.nxp.com.cn/docs/en/application-note/AN13651.pdf 26 AN13318 Power management solution for Horizon Journey 3 FS56/FS85 + PF81 + PF5024/PF52 Horizon Journey 2 ADAS https://www.nxp.com.cn/docs/en/application-note/AN13318.pdf 27 AN13863 NXP PMIC Solution for Black Sesame A1000L/A1000 Processor FS86 / FS56 + PF81 Black Sesame A1000 ADAS https://www.nxp.com/docs/en/application-note/AN13863.pdf 28 AN13748 NXP Power solution for Cypress Traveo II series MCU Application Note FS23,FS26 Cypress Traveo™ II Body https://www.nxp.com/webapp/Download?colCode=AN13748&appType=moderatedWithoutFAE
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TYPICAL PMIC BLOCK DIAGRAM: LOW VOLTAGE POWER MANAGEMENT ICs FOR i.MX: LOW VOLTAGE POWER MANAGEMENT ICs FOR NETWORKING: More information about the PMIC product ,pls find in the link below: https://www.nxp.com/docs/en/fact-sheet/PMICFS.pdf This document was generated from the following discussion: The specified discussion was not found.
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There are many members in the family of FS45&FS65, which you can choose the best for your application, you can see the rules of number definition and check the difference of different members from the picture below:                             More detailed, refer to :https://www.nxp.com/products/power-management/system-basis-chips/functional-safety-sbcs/grade-1-and-grade-0-safety-power-system-basis-chip-with-can-flexible-data-transceiver:FS6500?&tab=Documentation_Tab&linkline=Data-Sheet
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The latest version datasheet:https://www.nxp.com/docs/en/data-sheet/PF1510.pdf Board user guide:https://www.nxp.com/docs/en/user-guide/KTFRDMPF1510EVMUG.pdf EVM and Tools:https://www.nxp.com/products/power-management/pmics/power-management-for-i.mx-application-processors/power-management-integrated-circuit-pmic-for-low-power-application-processors:PF1510?tab=Design_Tools_Tab More information: https://www.nxp.com/products/power-management/pmics/power-management-for-i.mx-application-processors/power-management-integrated-circuit-pmic-for-low-power-application-processors:PF1510 This document was generated from the following discussion: PMIC PF1510 + I.MX Resource
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Hi     Here is a material to introduce use NXP tool to debug PF8x on customer board. Pls find in attach. BRs jinyu 
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  Table 1  NO Document and tool information Link to get the Tool  1 Latest version Datasheet  Datasheet 2 guidelines for QFN and SON packages AN1902 3 Schematic guidelines AN4717 4 Layout guidelines AN4622 5 MMPF0100 Errata for Mask 1N47F and 1N18J Errata 6 MMPF0100Z Errata for Mask 2N47F, 1N18J Errata 7 Features of Voltage Regulators AN4714 8 OTP Programming Instructions AN4536 9 Frequency Margining AN4840 10 KITPFPGMEVME Programmer(OTP programmer1) User guide Rev.A User guide Rev.B 11 KITPF0100SKTEVBE Programming Socket(OTP programmer2) User guide 12 GUI for the PF family development tools KITPFGUI 13 KITPFGUI 4.0 Graphical User Interface User guide 14 KITPFPGMEVME Evaluation Board Microcontroller Source Code Source Code 15 Gerber files for the KITPFPGMEVME Evaluation board (REVB) Design Tool 16 Gerber files for the KITPF0100SKTEVBE Evaluation boards Design Tool 17 KTPF0100UG, KITPF0100EPEVBE Evaluation Board User Guide 18 Gerber files for the KITPF0100EPEVBE Evaluation board(REVB) Design Tool 19 KITPF0200EPEVBE, Evaluation Board User Guide 20 Gerber files for the KITPF0200EPEVBE Evaluation board(REVD) Design Tool  
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More information ,pls find in:https://www.nxp.com/docs/en/brochure/SBCAUTOBRA4.pdf                                               Functional Safety SBCs|NXP  This document was generated from the following discussion: Safety SBCs Chosen for Automotive
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PCA9420 datasheet
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