qcvs ddr config screen : field <skew clk to dqs>

[stefanvranken]

Is this length-difference [mm] per bytelane between CLK-trace  and DQS[0:7]-trace ?
Or should I enter DQS-trace length [mm] ?

[stefanvranken]

Hello Pavel,
I think this number "skew CLK-to-DQS[0:7] in mm" to be entered in QCVS-ddr-tool is used to calculate the value of field WRLVLSTART in ddr-controller registers DDR_WRLVL_CNTL2/3 ?

Register DDR_WRLVL_CNTL has field WRTLVLSTART for DQS[0] I assume because P2020 reference manual shows just DQS here without [0] ?
WRLVLSTART for DQS[1 to 8] are in regs DDR_WRLVL_CNTL2 & 3.

Wite-levelling mechanism adjusts DQS-launch per bytelane (step 1/8 clk) to reach valid DQS - CLK timing a each dram-chip. Why is it necessary to have a WRLVLSTART value ? If I manually specify value 0000 then writelevelling starts searching over its entire range and will find adjustment value also ?

Does write-levelling overrule parameter WR_DAT_DELAY in register Timing_cfg_2 bits[19:21] ?  <<< Yes, see P2020RM page-385, Table 8-82, bit WRLVL_EN

WR_DAT_DELAY = wr-command to write-dq-dqs timing adjust = 1 clock delay   <<< my setting generated from QCVS-ddr-config

Regards, Stefan

[Pavel]

Look at the AN2582 about DDR layout rules:

http://cache.nxp.com/docs/en/application-note/AN2582.pdf?fsrch=1&sr=1&pageNum=1

See also AN2910:

http://cache.nxp.com/docs/en/application-note/AN2910.pdf?fsrch=1&sr=1&pageNum=1

and the AN5097:

http://cache.nxp.com/docs/en/application-note/AN5097.pdf?fsrch=1&sr=1&pageNum=1

Have a great day,
Pavel Chubakov

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