Hello,
What does RISC_ GPIO[x] mean in the "QUICC Engine Multiplex Options" table?
As the below table said, CE_PA24 has a sub-functionality named as RISC_CPIO[4]? what does it mean?
In the beginning, I think it means that CE_PA24 can be used as GPIO. But I also do a test by using CE_PA22,
although it does not have the GPIO sub-functionality, but it still can be used as GPIO, can output/input value.
So could you please help to clarify it?
Thank you,
Carl
Hello Pavel,
Thanks a lot for your clarification!
But I have a new question, as you said, prefixed with RISC_ means that the GPIO is belong to QE.
so, my question is that what is the different between QE GPIO and SOC GPIO, I found that both
these two kind of GPIO can be controlled by GUTS_DIR1n, GUTS_CPDATn, GUTS_CPPAR1n
register, so what is the character of QE GPIO?
Thank you,
Carl
The RISC_GPIO means that these pins are controlled by RISC QE engine and GPIO interface from the P1012 core.
Have a great day,
Pavel Chubakov
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The RISC_GPIO are the GPIOs those belong to Quicc Engine (QE). Since QE has a RISC (reduced instruction set computation) engine embedded inside so the to differentiate the QE's GPIOs from SoC GPIOs, the term RISC_ is prefixed for QE.
For example, RISC_GPIO[4] is multiplexed with CLK9 and BRGO2 on CE_PB24.
Have a great day,
Pavel Chubakov
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Note: If this post answers your question, please click the Correct Answer button. Thank you!
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