how to modify the norFlash size in boot start code?

[yinux]

ENV:

P2041e + NOR fLASH 128MB

mem:

0xFE00_0000 |  16MB | 0xFEFF_FFFF | CCSBAR

0xe800_0000 |  128MB | 0xeFFF_FFFF | NOR FLASH

1. when I edit the romInit.s， the system cannot be boot.

2. if I use the 0xff00_0000 |  16MB | 0xfFFF_FFFF | NOR FLASH cfg, in the romInit.s， then the system can be boot,  the ppc boot address must be 0xffff_fffc， so I think the norFLash address should be 0xf800_0000~0xffff_ffff, so I must move the CCSRBAR address.

would you please give me some suggestion?  I want to use the 128MB norFlash as the boot flash.

Try my best to modify the CCSRBAR address, but no useless, i donot know the reason.

the CCSBAR_RESET is 0xfe000000, the CCSBAR is 0xf0000000, I want to move the ccsrbar address space ,So  I could use the 0xf800_0000~0xffff_ffff as to the nor flash address.

the code as follows:

WRITEADR(r6,r7,P2041_LAWBARL7(CCSBAR_RESET),CCSBAR)

    WRITEADR(r6,r7,P2041_LAWAR7(CCSBAR_RESET),

   LAWAR_ENABLE | LAWAR_TGTIF_RESERVE | LAWAR_SIZE_16MB )

    LOADVAR(r7, P4080_LAWAR8(CCSBAR_RESET))

    isync 

    lis     r7,HI(CCSBAR_RESET)

    ori     r7,r7,LO(CCSBAR_RESET)

    lwz     r4, (CCSRBARH_OFFSET)(r7)

    lis     r7,HI(CCSBAR_RESET)

    ori     r7,r7,LO(CCSBAR_RESET)

    lwz     r4, (CCSRBARL_OFFSET)(r7)

    lis     r6,HI(CCSBAR)

    ori     r6,r6, LO(CCSBAR)

    xor     r5,r5,r5

    lis     r7,HI(CCSBAR_RESET)

    ori     r7,r7,LO(CCSBAR_RESET)

    stw     r5,(CCSRBARH_OFFSET)(r7)

    stw     r6,(CCSRBARL_OFFSET)(r7)

    sync

    lis     r5,HI(CCSBAR_COMMIT)

    ori     r5,r5, LO(CCSBAR_COMMIT)

    stw     r5,(CCSRAR_OFFSET)(r7)

    sync

    WRITEADR(r6,r7,P2041_LAWBARL7 (CCSBAR),0x0)

    sync

    WRITEADR(r6,r7,P2041_LAWAR7 (CCSBAR),0x0)

    LOADVAR(r7, P2041_LAWAR7 (CCSBAR))

    isync  

[yipingwang · Accepted solution]

Hello Yang Yang,

I checked SDK 1.8 u-boot source code, I don't think you need to modify the source code to make it suitable for your 128MB NOR Flash, 256M NOR Flash space has already been allocated in LAW and TLB entries configuration in the u-boot source.

1. Address allocation

Physical Address:

NOR Flash: 0xf_e000_0000-0xf_efff_ffff(256M)

CCSRBAR: 0x0_FE00_0000

Effective Address:

NOR Flash: 0xe800_0000-0xefff_ffff

CCSRBAR: 0xfe00_0000

Note: In PowerPC architecture, effective address is used by the program, and the TLB entry define the map between the effective address and physical address.

So there is no address conflict at all.

2. The 4K boot page

In PowerPC, when each core comes out of reset, its MMU has one default 4K boot page defined at 0xFFFF_Fnnn, each core begins execution with the instruction at effective address 0xFFFF_FFFC. So in the default 4K boot page TLB entry, the effective address is 0xFFFF_Fnnn, the physical address is boot ROM physical address, it is configured by hardware.

3. If you want to modify the address definition, it is not recommended to modify the c(.s) code directly, you could modify the header file include/configs/P2041RDB.h, include/configs/corenet_ds.h or ./arch/powerpc/include/asm/mmu.h.

Have a great day,
Yiping

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[yinux]

thanks for your quick response.

1. So in the default 4K boot page TLB entry, the effective address is 0xFFFF_Fnnn, the physical address is boot ROM physical address, it is configured by hardware.  

[yang] how to config the physical address by hardware?

          in the p2041.reg file, 

SCGA LA               LAWBARH0                            00000C00  00000000       LA               /ua:0

SCGA LA               LAWBARL0                            00000C04  E0000000       LA               /ua:0

SCGA LA               LAWAR0                                00000C08  81F0001B       LA               /ua:0

SCGA ELBC             BR0                                     00124000  E8001001       ELBC             /ua:0

SCGA ELBC             OR0                                     00124004  F8000F85       ELBC             /ua:0

      so the physical address: 0x0_e000_0000 ~ 0x0_efff_ffff, 256MB ?

                 effective address: 0x0_e800_0000_0x0_efff_ffff, 128MB

    I program the bootrom.bin in the 0xeff0_0000~0xefff_fffff,  how to map the address 0xefff_ffff to the 0xffff_ffff ? I am confused.

2. i use the vxworks bootrom, which may be the same theory with the uboot,

    in my code , 

    FLASH_BASE_ADRS    0xff00_0000 ~0xffff_ffff ,16MB;

    ROM_TEXT_ADRS       0xfff0_0100

    now I want to expand the nor flash size,  edit as follows:

     in the bootcode:

      1)       

             LAWBARH0                            00000C00  00000000  

             LAWBARL0                            00000C04  E0000000 

             LAWAR0                                00000C08  81F0001B    

             BR0                                     00124000  E8001001   

             OR0                                     00124004  F8000F85  

          FLASH_BASE_ADRS    0xe800_0000 ~0xefff_ffff ,128MB;

             ROM_TEXT_ADRS       0xeff0_0100

     2) flash TLB:

addis  r4,0,0x1000           /* TLBSEL = TLB1(CAM) , ESEL = 0 */

    ori    r4,r4,0x0000

    addis  r5, 0, HI(MMU_STATE_VALID|MMU_STATE_IPROT)

    ori    r5,r5,_MMU_TLB_SZ_256M  /* TS = 0, TSIZE = 256MByte page size*/

    addis  r6, 0, HI(FLASH_BASE_ADRS)   /* EPN */

    ori    r6,r6,MMU_ROM_ACCESS

    addis  r7, 0, HI(FLASH_BASE_ADRS)   /* RPN */

    ori    r7,r7,0x0015          /* Supervisor XWR*/

     3)   edit the boot Space Translation

         BSTRL      00000C24   0xefff_f000

         BSTAR     00000C28   0x8100_000b

        now the the effective address is 0xefff_fffc?

would you please give me some suggestion?

thanks very much.

[yipingwang]

Hello yangyang,

1. When each core just comes out of reset, only one TLB entry is configured, this is the default 4K boot page, and instructions of u-boot cannot exceed this 4K boot page range at first, then in the following code execution u-boot configures other MMU TLB entries for NOR Flash, DDR, CCSR, PCIe etc.

According to your LAW configuration for NOR Flash, the physical address has already been allocated at 0x0_e000_0000 ~ 0x0_efff_ffff. If your target is configured as boot from NOR Flash, the effective address of 4K TLB entry is 0xFFFF_F000, the physical address is 0x0_efff_f000.

You also need to program u-boot image to NOR Flash carefully to make sure the first execution instruction is u-boot reset vector(0x_efff_fffc).

2.

1)and 2) It looks your configurations make sense.

3)Why do you need to configure of Boot Space Translation registers?

Each core begins execution with the instruction at effective address 0xFFFF_FFFC, for your system, if boot code resides at a different physical address you need to to use boot space translation feature.

For example, as usual the effective address of the first execution instruction is 0xFFFF_FFFC, and it corresponds to the physical address 0x0_efff_fffc, on NOR Flash this address should be the reset vector instruction. But due to your improper design, the reset vector is not placed at the physical address 0x0_efff_fffc, it is located at 0x0_e8ff_fffc, you need to configure boot space translation registers to make the system to fetch the instruction from physical address 0x0_e8ff_fffc. These Boot Space Translation registers should takes effective on physical addresses, the effective of the default 4K boot page is 0xFFFF_F000~0xFFFF_FFFF, this is considered fixed.

Have a great day,
Yiping

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[yinux]

thanks .

1.  in your opinion "You also need to program u-boot image to NOR Flash carefully to make sure the first execution instruction is u-boot reset vector(0x_efff_fffc)."

     how to do it ?

   when I debug the bootrom, i see the cpu reset, then jump address      0xffff_fffc:      b 0x ffff_f800?

[yipingwang]

Hello Yang Yang,

In u-boot, the first instruction is  "b _start_e500", please check whether 0xffff_f800 is code start address.

You could use the following command to get the disassembly file

powerpc-fsl-linux-objdump -d <elf_file> >a.txt

If you need my assistance, please attach the output text file.

Thanks,

Yiping

[yinux]

thanks Yiping,  my boot binary is bootrom, I use the following command to generate the disabssemble file, please check it.

1. nmppc bootrom_uncmp > b.txt
2. objdumpppc --disassemble-all --show-raw-insn bootrom_uncmp> a.txt

[yipingwang]

Hello Yang Yang,

The jump address is correct, it is "_resetEntry", you could continue to debug u-boot.

Thanks,

Yiping

[yinux]

thanks for your reply.

I try to edit the CCSBAR space,   something is wrong.    follow the  P2040RM.pdf   4.3.1.1 Updating CCSRBARs

1)  norFlash law: 0xff00_0000~0xffff_ffff

2) CCSRBAR_RESET : 0xFE00_0000

    my new CCSRBAR address: 0xf000_0000

   when debug,  "stw     r7,0(r6) " will failed,  I donot know the reason?   

fffffa60:   lis     r6,0xFE000C84@h

fffffa64:   ori     r6,r6,0xFE000C84@l

fffffa68:   lis     r7,0xF0000000@h

fffffa6c:   ori     r7,r7,0xF0000000@l

fffffa70:   stw     r7,0(r6)

fffffa74:   msync

[yipingwang]

Hello Yang Yang,

Please refer to the following template.

Write new value to CCSRBAR:

        #define CCSRAR_C        0x80000000

        lis r0, CONFIG_SYS_CCSRBAR_PHYS_HIGH@h

        ori r0, r0, CONFIG_SYS_CCSRBAR_PHYS_HIGH@l

        lis r1, CONFIG_SYS_CCSRBAR_PHYS_LOW@h

        ori r1, r1, CONFIG_SYS_CCSRBAR_PHYS_LOW@l

        lis r2, CCSRAR_C@h

        ori r2, r2, CCSRAR_C@l

        stw r0, 0(r9)      /* Write to CCSRBARH */

        sync                    /* Make sure we write to CCSRBARH first */

        stw r1, 4(r9)      /* Write to CCSRBARL */

        sync

        /*

        * Write a 1 to the commit bit (C) of CCSRAR at the old location.

        * Follow this with a sync instruction.

        */

        stw r2, 8(r9)

        sync

Create LAW:

        lis    r0, CONFIG_SYS_CCSRBAR_PHYS_HIGH@h

        ori r0, r0, CONFIG_SYS_CCSRBAR_PHYS_HIGH@l

        lis r1, CONFIG_SYS_CCSRBAR_PHYS_LOW@h

        ori r1, r1, CONFIG_SYS_CCSRBAR_PHYS_LOW@l

        lis r2, CCSRBAR_LAWAR@h

        ori r2, r2, CCSRBAR_LAWAR@l

        stw r0, 0xc00(r9)  /* LAWBARH0 */

        stw r1, 0xc04(r9)  /* LAWBARL0 */

        sync

        stw r2, 0xc08(r9)  /* LAWAR0 */

Have a great day,
Yiping

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[yinux]

I am sorry,something disturb my test last week.

In your opinion, the register r9 which is the CCSRBAR_RESET register?