Trouble with NAND bad block table

cancel
Showing results for 
Search instead for 
Did you mean: 

Trouble with NAND bad block table

Jump to solution
2,900 Views
yensid
Contributor III

Hi I'm working with a custom board based off of the P1010RDB.  We are booting from NAND and are using Micron MT29F8G08ABABA as a replacement NAND.  I can program the nand using jtag and uboot recognizes the NAND, after some minor changes. Uboot successfully boots to the command prompt.  During boot "Bad block table not found for chip 0  No space left to write bad block table" is displayed and I cannot write to the nand chip from u-boot to save the environment or program new u-boot. The chip is 1GByte and has a 512K block size, and 4K pagesize with 224byte oob size.

If I run nand bad the whole flash chip is reported as bad.

Has anyone had a similar experiance?  Any ideas what might be causing this?

Thanks for your help.

Code Changes to nand_ids.c

{"NAND 1GiB 3,3V 8-bit Custom",0x38, 0, 1024, 0, LP_OPTIONS}

Code Changes nand_boot.c:

U-boot Output:

/* Check Micron device */
/* Check for 5 byte ID + Micron + read more 0x00 */
else if (id_data[0] == NAND_MFR_MICRON && id_data[4] != 0x00
&& id_data[5] == 0x00
&& id_data[6] == 0x00) {

/* Calc pagesize */
mtd->writesize = 1024 << (extid & 0x03);
extid >>= 2;

/* OOB is 218B/224B per 4KiB pagesize */
mtd->oobsize = ((extid & 0x03) == 0x03 ? 218 :
224) << (mtd->writesize >> 13);
extid >>= 3;
/* Blocksize is multiple of 64KiB */
mtd->erasesize = mtd->writesize <<
(extid & 0x03) << 6;
/* All Micron have busw x8? */
busw = 0;

printf("Micron id_data[0] = 0x%X, id_data[1] = 0x%X\n", id_data[0], id_data[1]);
printf("Micron mtd->erasesize (block):%d\n", mtd->erasesize);
printf("Micron mtd->writesize (page):%d\n", mtd->writesize);
printf("Micron mtd->oobsize:%d\n", mtd->oobsize);

}

NAND boot...

U-Boot 2013.01-dirty (Nov 20 2013 - 15:55:35)

CPU:   P1010, Version: 1.0, (0x80f10010)

Core:  E500, Version: 5.1, (0x80212151)

Clock Configuration:

       CPU0:800  MHz,

       CCB:400  MHz,

       DDR:333.333 MHz (666.667 MT/s data rate) (Asynchronous), IFC:100  MHz

L1:    D-cache 32 kB enabled

       I-cache 32 kB enabled

Board: P1010RDB

I2C:   ready

SPI:   ready

DRAM:  Detected UDIMM Fixed DDR on board

1 GiB (DDR3, 32-bit, CL=5, ECC off)

Now running in RAM - U-Boot at: 3ff30000

L2:    256 KB enabled

NAND: 

**** Additional Debug Information added ***

Micron id_data[0] = 0x2C, id_data[1] = 0x38

Micron mtd->erasesize (block):524288

Micron mtd->writesize (page):4096

Micron mtd->oobsize:224

1024 MiB

MMC:  FSL_SDHC: 0

Bad block table not found for chip 0

Bad block table not found for chip 0

No space left to write bad block table

*** Warning - readenv() failed, using default environment

PCIe1: Root Complex of mini PCIe Slot, no link, regs @ 0xffe0a000

PCIe1: Bus 00 - 00

PCIe2: Root Complex of PCIe Slot, no link, regs @ 0xffe09000

PCIe2: Bus 01 - 01

In:    serial

Out:   serial

Err:   serial

Net:   PHY reset timed out

PHY reset timed out

eTSEC1 [PRIME], eTSEC2, eTSEC3

Hit any key to stop autoboot:  0

=> saveenv

Saving Environment to NAND...

Erasing Nand...

Skipping bad block at  0x00100000                                         

Skipping bad block at  0x00180000                                         

Skipping bad block at  0x00200000                                         

Writing to Nand... FAILED!

=> nand info

Device 0: nand0, sector size 512 KiB

  Page size      4096 b

  OOB size        224 b

  Erase size   524288 b

=>

Labels (1)
0 Kudos
1 Solution
324 Views
yipingwang
NXP TechSupport
NXP TechSupport

Please refer to the following Patch of P1010RDB-PB with MT29F16G08ABABAWP NAND.

/* old board P1010RDB uses 512M NAND */

/* new board P1010RDB-PB uses 4k-pagesize NAND 2GByte MT29F16G08ABABAWP NAND */

diff --git a/include/configs/P1010RDB.h b/include/configs/P1010RDB.h

index ba3f7c2..f2493c5 100644

--- a/include/configs/P1010RDB.h

+++ b/include/configs/P1010RDB.h

/*

  * IFC Definitions

  */

@@ -322,6 +321,8 @@ extern unsigned long get_sdram_size(void);

                                | CSPR_MSEL_NAND        \

                                | CSPR_V)

#define CONFIG_SYS_NAND_AMASK  IFC_AMASK(64*1024)

+

+#if defined(CONFIG_P1010RDB)

#define CONFIG_SYS_NAND_CSOR   (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \

                                | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \

                                | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \

@@ -329,13 +330,25 @@ extern unsigned long get_sdram_size(void);

                                | CSOR_NAND_PGS_512     /* Page Size = 512b */ \

                                | CSOR_NAND_SPRZ_16     /* Spare size = 16 */ \

                                | CSOR_NAND_PB(32))     /* 32 Pages Per Block */

+#define CONFIG_SYS_NAND_BLOCK_SIZE     (16 * 1024)

+#elif defined(CONFIG_P1010RDB_PB)

+#define CONFIG_SYS_NAND_ONFI_DETECTION

+#define CONFIG_SYS_NAND_CSOR   (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \

+                               | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \

+                               | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \

+                               | CSOR_NAND_RAL_3       /* RAL = 3Byes */ \

+                               | CSOR_NAND_PGS_4K      /* Page Size = 4K */ \

+                               | CSOR_NAND_SPRZ_224    /* Spare size = 224 */ \

+                               | CSOR_NAND_PB(128))  /*Pages Per Block = 128 */

+#define CONFIG_SYS_NAND_BLOCK_SIZE     (512 * 1024)

+#endif

#define CONFIG_SYS_NAND_BASE_LIST      { CONFIG_SYS_NAND_BASE }

#define CONFIG_SYS_MAX_NAND_DEVICE     1

#define CONFIG_MTD_NAND_VERIFY_WRITE

  #define CONFIG_CMD_NAND

-#define CONFIG_SYS_NAND_BLOCK_SIZE     (16 * 1024)

+#if defined(CONFIG_P1010RDB)

/* NAND Flash Timing Params */

#define CONFIG_SYS_NAND_FTIM0          FTIM0_NAND_TCCST(0x01) | \

                                        FTIM0_NAND_TWP(0x0C)   | \

@@ -349,6 +362,22 @@ extern unsigned long get_sdram_size(void);

                                        FTIM2_NAND_TREH(0x05) | \

                                        FTIM2_NAND_TWHRE(0x0f)

#define CONFIG_SYS_NAND_FTIM3          FTIM3_NAND_TWW(0x04)

+#elif defined(CONFIG_P1010RDB_PB)

+/* support MT29F16G08ABABAWP 4k-pagesize 2G-bytes NAND */

+/* ONFI NAND Flash mode0 Timing Params */

+#define CONFIG_SYS_NAND_FTIM0  (FTIM0_NAND_TCCST(0x07)| \

+                                       FTIM0_NAND_TWP(0x18)   | \

+                                       FTIM0_NAND_TWCHT(0x07) | \

+                                       FTIM0_NAND_TWH(0x0a))

+#define CONFIG_SYS_NAND_FTIM1  (FTIM1_NAND_TADLE(0x32)| \

+                                       FTIM1_NAND_TWBE(0x39)  | \

+                                       FTIM1_NAND_TRR(0x0e)   | \

+                                       FTIM1_NAND_TRP(0x18))

+#define CONFIG_SYS_NAND_FTIM2  (FTIM2_NAND_TRAD(0x0f) | \

+                                       FTIM2_NAND_TREH(0x0a)  | \

+                                       FTIM2_NAND_TWHRE(0x1e))

+#define CONFIG_SYS_NAND_FTIM3  0x0

+#endif

#define CONFIG_SYS_NAND_DDR_LAW                11

#ifdef CONFIG_MMC

#define CONFIG_CMD_MMC

#define CONFIG_DOS_PARTITION

@@ -613,9 +647,14 @@ extern unsigned long get_sdram_size(void);

#define CONFIG_ENV_SIZE                0x2000

#elif defined(CONFIG_NAND)

#define CONFIG_ENV_IS_IN_NAND

+#if defined(CONFIG_P1010RDB)

#define CONFIG_ENV_SIZE                CONFIG_SYS_NAND_BLOCK_SIZE

+#define CONFIG_ENV_RANGE       (3 * CONFIG_ENV_SIZE) /* 3*16=48K for env */

+#elif defined(CONFIG_P1010RDB_PB)

+#define CONFIG_ENV_SIZE                (16 * 1024)

+#define CONFIG_ENV_RANGE       (32 * CONFIG_ENV_SIZE) /* new block size 512K */

+#endif

#define CONFIG_ENV_OFFSET      ((512 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE)

-#define CONFIG_ENV_RANGE       (3 * CONFIG_ENV_SIZE)

#elif defined(CONFIG_SYS_RAMBOOT)

#define CONFIG_ENV_IS_NOWHERE          /* Store ENV in memory only */

#define CONFIG_ENV_ADDR                        (CONFIG_SYS_MONITOR_BASE - 0x1000)

View solution in original post

0 Kudos
3 Replies
324 Views
yensid
Contributor III

I have a follow up question. NAND now fully works but on boot there is a message "fsl_ifc_read_buf beyond end of buffer (256 requested, 0 available)".  This message originates from fsl_ifc_nand.c. Do you know what the cause of this message is? 

Thanks again.

Uboot Output:

NAND boot...

U-Boot 2013.01-dirty (Nov 22 2013 - 16:30:00)

CPU:   P1010, Version: 1.0, (0x80f10010)

Core:  E500, Version: 5.1, (0x80212151)

Clock Configuration:

       CPU0:800  MHz,

       CCB:400  MHz,

       DDR:333.333 MHz (666.667 MT/s data rate) (Asynchronous), IFC:100  MHz

L1:    D-cache 32 kB enabled

       I-cache 32 kB enabled

Board: P1010RDB

I2C:   ready

SPI:   ready

DRAM:  Detected UDIMM Fixed DDR on board

1 GiB (DDR3, 32-bit, CL=5, ECC off)

Now running in RAM - U-Boot at: 3ff30000

L2:    256 KB enabled

NAND: 

** ADDED Debug**

len = 256 ctrl->read_bytes = 256 ctrl->index = 256

ctrl->oob = 0 ctrl->eccread = 0

len = 256 ctrl->read_bytes = 256 ctrl->index = 256

ctrl->oob = 0 ctrl->eccread = 0

fsl_ifc_read_buf beyond end of buffer (256 requested, 0 available)

** ADDED Debug**

len = 256 ctrl->read_bytes = 256 ctrl->index = 256

ctrl->oob = 0 ctrl->eccread = 0

fsl_ifc_read_buf beyond end of buffer (256 requested, 0 available)

Micron id_data[0] = 0x2C, id_data[1] = 0x38

Micron mtd->erasesize (block):524288

Micron mtd->writesize (page):4096

Micron mtd->oobsize:224

Micron mtd->oobavail:0

1024 MiB

MMC:  FSL_SDHC: 0

PCIe1: Root Complex of mini PCIe Slot, no link, regs @ 0xffe0a000

PCIe1: Bus 00 - 00

PCIe2: Root Complex of PCIe Slot, no link, regs @ 0xffe09000

PCIe2: Bus 01 - 01

In:    serial

Out:   serial

Err:   serial

Net:   PHY reset timed out

PHY reset timed out

eTSEC1 [PRIME], eTSEC2, eTSEC3

Hit any key to stop autoboot:  0

=>

0 Kudos
325 Views
yipingwang
NXP TechSupport
NXP TechSupport

Please refer to the following Patch of P1010RDB-PB with MT29F16G08ABABAWP NAND.

/* old board P1010RDB uses 512M NAND */

/* new board P1010RDB-PB uses 4k-pagesize NAND 2GByte MT29F16G08ABABAWP NAND */

diff --git a/include/configs/P1010RDB.h b/include/configs/P1010RDB.h

index ba3f7c2..f2493c5 100644

--- a/include/configs/P1010RDB.h

+++ b/include/configs/P1010RDB.h

/*

  * IFC Definitions

  */

@@ -322,6 +321,8 @@ extern unsigned long get_sdram_size(void);

                                | CSPR_MSEL_NAND        \

                                | CSPR_V)

#define CONFIG_SYS_NAND_AMASK  IFC_AMASK(64*1024)

+

+#if defined(CONFIG_P1010RDB)

#define CONFIG_SYS_NAND_CSOR   (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \

                                | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \

                                | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \

@@ -329,13 +330,25 @@ extern unsigned long get_sdram_size(void);

                                | CSOR_NAND_PGS_512     /* Page Size = 512b */ \

                                | CSOR_NAND_SPRZ_16     /* Spare size = 16 */ \

                                | CSOR_NAND_PB(32))     /* 32 Pages Per Block */

+#define CONFIG_SYS_NAND_BLOCK_SIZE     (16 * 1024)

+#elif defined(CONFIG_P1010RDB_PB)

+#define CONFIG_SYS_NAND_ONFI_DETECTION

+#define CONFIG_SYS_NAND_CSOR   (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \

+                               | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \

+                               | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \

+                               | CSOR_NAND_RAL_3       /* RAL = 3Byes */ \

+                               | CSOR_NAND_PGS_4K      /* Page Size = 4K */ \

+                               | CSOR_NAND_SPRZ_224    /* Spare size = 224 */ \

+                               | CSOR_NAND_PB(128))  /*Pages Per Block = 128 */

+#define CONFIG_SYS_NAND_BLOCK_SIZE     (512 * 1024)

+#endif

#define CONFIG_SYS_NAND_BASE_LIST      { CONFIG_SYS_NAND_BASE }

#define CONFIG_SYS_MAX_NAND_DEVICE     1

#define CONFIG_MTD_NAND_VERIFY_WRITE

  #define CONFIG_CMD_NAND

-#define CONFIG_SYS_NAND_BLOCK_SIZE     (16 * 1024)

+#if defined(CONFIG_P1010RDB)

/* NAND Flash Timing Params */

#define CONFIG_SYS_NAND_FTIM0          FTIM0_NAND_TCCST(0x01) | \

                                        FTIM0_NAND_TWP(0x0C)   | \

@@ -349,6 +362,22 @@ extern unsigned long get_sdram_size(void);

                                        FTIM2_NAND_TREH(0x05) | \

                                        FTIM2_NAND_TWHRE(0x0f)

#define CONFIG_SYS_NAND_FTIM3          FTIM3_NAND_TWW(0x04)

+#elif defined(CONFIG_P1010RDB_PB)

+/* support MT29F16G08ABABAWP 4k-pagesize 2G-bytes NAND */

+/* ONFI NAND Flash mode0 Timing Params */

+#define CONFIG_SYS_NAND_FTIM0  (FTIM0_NAND_TCCST(0x07)| \

+                                       FTIM0_NAND_TWP(0x18)   | \

+                                       FTIM0_NAND_TWCHT(0x07) | \

+                                       FTIM0_NAND_TWH(0x0a))

+#define CONFIG_SYS_NAND_FTIM1  (FTIM1_NAND_TADLE(0x32)| \

+                                       FTIM1_NAND_TWBE(0x39)  | \

+                                       FTIM1_NAND_TRR(0x0e)   | \

+                                       FTIM1_NAND_TRP(0x18))

+#define CONFIG_SYS_NAND_FTIM2  (FTIM2_NAND_TRAD(0x0f) | \

+                                       FTIM2_NAND_TREH(0x0a)  | \

+                                       FTIM2_NAND_TWHRE(0x1e))

+#define CONFIG_SYS_NAND_FTIM3  0x0

+#endif

#define CONFIG_SYS_NAND_DDR_LAW                11

#ifdef CONFIG_MMC

#define CONFIG_CMD_MMC

#define CONFIG_DOS_PARTITION

@@ -613,9 +647,14 @@ extern unsigned long get_sdram_size(void);

#define CONFIG_ENV_SIZE                0x2000

#elif defined(CONFIG_NAND)

#define CONFIG_ENV_IS_IN_NAND

+#if defined(CONFIG_P1010RDB)

#define CONFIG_ENV_SIZE                CONFIG_SYS_NAND_BLOCK_SIZE

+#define CONFIG_ENV_RANGE       (3 * CONFIG_ENV_SIZE) /* 3*16=48K for env */

+#elif defined(CONFIG_P1010RDB_PB)

+#define CONFIG_ENV_SIZE                (16 * 1024)

+#define CONFIG_ENV_RANGE       (32 * CONFIG_ENV_SIZE) /* new block size 512K */

+#endif

#define CONFIG_ENV_OFFSET      ((512 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE)

-#define CONFIG_ENV_RANGE       (3 * CONFIG_ENV_SIZE)

#elif defined(CONFIG_SYS_RAMBOOT)

#define CONFIG_ENV_IS_NOWHERE          /* Store ENV in memory only */

#define CONFIG_ENV_ADDR                        (CONFIG_SYS_MONITOR_BASE - 0x1000)

View solution in original post

0 Kudos
324 Views
yensid
Contributor III

Thanks Yiping! :smileyhappy: That solved the issue.

0 Kudos