Time Base registers TBL & TBU

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Time Base registers TBL & TBU

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benjaminchauvel
Contributor I

i'd like to use the Time Base registers to capture time in my software.

i'm using the HID0[SEL_TBCLK]=0 so the TB is updated every 8 core complex bus (CCB) clocks.

my question is : How can i read the TBU and TBL at the same time so i have a good correlation between the 2 registers value ?


Some processors i worked with have some kind of freezing mechanism, but i don't see anything like like for the P2020.

in §4.7.3, the EREF_RM describes a 64-bit mode for spr 268 (TBL)  in order to read the TB. Is it possible on P2020 ?


Thanks.

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alexander_yakov
NXP Employee
NXP Employee

It is not possible to read the entire 64-bit timebase value by one instruction, instruction mfspr reads only 32 bits. The following is said in "Book E: Enhanced PowerPC Architecture", Section 8.4.3 "Reading the Time Base":

 

It is not possible to read the entire 64-bit Time Base in a single instruction. mfspr RT, TBL moves from the lower half of the Time Base (TBL) to a GPR, and mfspr RT, TBU extended mnemonic moves from the upper half (TBU) to a GPR. Because of the possibility of a carry from Time Base Lower to Time Base Upper occurring between reads of Time Base Lower and Time Base Upper, a sequence such as the following is necessary to read the Time Base.

 

loop:

mfspr Rx,TBU #load from TBU

mfspr Ry,TBL #load from TBL

mfspr Rz,TBU #load from TBU

cmp cr0,0,Rz,Rx #see if 'old' = 'new'

bc 4,2,loop #loop if carry occurred

 

The comparison and loop are necessary to ensure that a consistent pair of values has been obtained.

Reading entire 64-bit by one instruction is possible in 64-bit implementations only.

P2020 device (e500v2 core) is 32-bit.


Have a great day,
Alexander
TIC

 

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benjaminchauvel
Contributor I

thank you !

i've totality missed that book. I thought the EREF_RM was the book E.

I would never have asked my question if i had this one.

Maybe you should add it to the documentation page.

Benjamin.

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alexander_yakov
NXP Employee
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This document is publicly available on our site.

Here is a direct link:

https://www.nxp.com/docs/en/user-guide/BOOK_EUM.pdf 

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alexander_yakov
NXP Employee
NXP Employee

It is not possible to read the entire 64-bit timebase value by one instruction, instruction mfspr reads only 32 bits. The following is said in "Book E: Enhanced PowerPC Architecture", Section 8.4.3 "Reading the Time Base":

 

It is not possible to read the entire 64-bit Time Base in a single instruction. mfspr RT, TBL moves from the lower half of the Time Base (TBL) to a GPR, and mfspr RT, TBU extended mnemonic moves from the upper half (TBU) to a GPR. Because of the possibility of a carry from Time Base Lower to Time Base Upper occurring between reads of Time Base Lower and Time Base Upper, a sequence such as the following is necessary to read the Time Base.

 

loop:

mfspr Rx,TBU #load from TBU

mfspr Ry,TBL #load from TBL

mfspr Rz,TBU #load from TBU

cmp cr0,0,Rz,Rx #see if 'old' = 'new'

bc 4,2,loop #loop if carry occurred

 

The comparison and loop are necessary to ensure that a consistent pair of values has been obtained.

Reading entire 64-bit by one instruction is possible in 64-bit implementations only.

P2020 device (e500v2 core) is 32-bit.


Have a great day,
Alexander
TIC

 

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Note: If this post answers your question, please click the Correct Answer button. Thank you!
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