PLL lock on P1020

[bfac]

Hello!

Is there a way we can internally probe (register, etc) if a given clock PLL is locked and working fine on P1020?

We are having issues detecting a PCIe device, we believe this is caused by a deviation on the SerDes "SD_REF_CLK", this clock is derived from the main processor PLL.

Thanks!

Bruno

[alexander_yakov]

SD_REF_CLK is input clock, it is not derived from the main processor PLL