Is 0 a permissible value for SDLKFS in the eMMC System Control register?

[eugenemalina]

In P1010 QorIQ Ref Manual the minimal value for SDCLKFS is 0x01. This means that the base clock will be divided by at 2 at the minimum. The question is if I specify the value as 0x00 will the division occur?

clock freq = base clock /( (vv*2)*(x+1) )

where vv is the SDCLKFS value and x is the divisor. I my case the base clock is 200MHz and I need to set clock frequency to 40MHz. If ww=0 is a valid value I can set x=4 and get 40MHz, otherwise I do not see how it is possbile.

Any advice will be appreciated.

[andrei_skok · Accepted solution]

According to the latest P1010RM, table eSDHC_SYSCTL field descriptions:

SDCLK frequency select. This register is used to select the frequency of the SDCLK pin. The frequency is not programmed directly, rather this register holds the prescaler (this register) and divisor (next register) of the base clock frequency register.

Setting 0x00 bypasses the frequency prescaler of the SD clock. Multiple bits must not be set, or the behavior of this prescaler is undefined. The two default divider values can be calculated by the frequency of the base clock (ipg_perclk) and the following divisor bits.

The frequency of SDCLK is set by the following formula: Clock Frequency = (Base Clock) ÷ (prescaler x divisor)

For example, if the base clock frequency is 96 MHz and the target frequency is 25 MHz, then choosing the prescaler value of 0x01 and divisor value of 0x1 will yield 24 MHz, which is the nearest frequency less than or equal to the target. Similarly, to approach a clock value of 400 kHz, the prescaler value of 0x08 and divisor value of 0xE yields the exact clock value of 400 kHz. The reset value of this bit field is 0x80, so if the input base clock (ipg_perclk) is about 96 MHz, the default SD clock after reset is 375 kHz. The programmed SD Clock frequency shall never exceed maximum SD clock supported by the card.

NOTE: Both DVS and SDCLKFS fields should not be programmed 0 simultaneously.

Only the following settings are allowed:

0x00 Base clock

0x01 Base clock divided by 2

0x02 Base clock divided by 4

0x04 Base clock divided by 8

0x10 Base clock divided by 32

0x08 Base clock divided by 16

0x20 Base clock divided by 64

0x40 Base clock divided by 128

0x80 Base clock divided by 256

SDCLKFS = 0x00 means Base clock divided by 1 and you can use SDCLKFS = 0x00 and DVS = 0x04 to get 40MHz from the 200MHz base clock.