TEF8101 ADC data error?

[longfeiwang]

I am using TEF8101 (LVDS interface),When I set the decimation rate to 1, the ADC equivalent sampling rate is 40MHZ,The ADC data (DC component 2048 has been subtracted) seems to have a lot of sudden changes(-2048\-2045...), such as the figure below.

If I change the decimation rate to 2 and the equivalent sampling rate is 20MHZ, the abrupt data will not exist.

Has some filtering been done in the PDC?

[petervlna · Accepted solution]

Hello,

Could you please explain what your are intending to do?

Decimation factor of 1 is for test purposes only, as stated in the datasheet

Best regards,

Peter

[longfeiwang]

The problem has been solved. After modifying the FPGA LVDS timing, the abrupt data no longer exists