Register Access in S32G-VNP-RDB32 (SJA1110) Switch

[Atkinson]

Hi,
I am looking to write the values into the Register 
can you give me the complete address for Reading and writing 
Address Name Access Reset Description
8Ch DYN_BE_LKP_
ENTRY0
R/W 0h
(FFFFFFFEh)

before 8ch  what would be the base address?
like for example it will have 0x3fc0008c so for this dynamic entry table we will have a complete address can you give me the complete address for 
8Ch DYN_BE_LKP_
ENTRY0
R/W 0h
(FFFFFFFEh)
90h DYN_BE_LKP_
ENTRY1
R/W 0h
94h DYN_BE_LKP_
ENTRY2
R/W 0h
98h DYN_BE_LKP_
ENTRY3
R/W 0h
9Ch DYN_BE_LKP_
ENTRY4
R/W 0h
A0h DYN_BE_LKP_
ENTRY5
R/W 0h
A4h DYN_BE_LKP_CTRL R/W 0h
(FF800000h)

can you Provide me the full address for configuring the Dynamic Entry in the register ?

and where this implementation need to be take place in SJA1110 Switch 

[PavelL · Accepted solution]

Hello @Atkinson ,

I understand it might not seem straightforward at first, but the concept is actually quite simple.

The final register address depends on the access method - whether you're accessing it internally via the M7 core over AHB, or externally via the SPI_AP interface. The base addresses differ depending on the access point.

The register address is calculated using the base address provided in Table 2 of UM11107. For example, for the switch subsystem, the base address is 0x00000000 for SPI_AP access and 0xFF000000 for AHB access.

In your case, the register 0x8C (DYN_BE_LKP_ENTRY0) becomes 0xFF00008C when accessed via AHB.

Now, here’s where it might get confusing: the SDK driver defines the following:

#define SJA1110_L2_ART_LE_ADDR (0x3fc00023) /**< Address of the l2ArtLockedEntry register *

The SWITCH_DRV_Write routine shifts the address left by 2 bits (<< 2) for internal (AHB) access. For SPI transfers (used in cascaded switch setups), no shift is applied. So, 0x3fc00023 << 2 results in 0xFF00008C.

I hope that with the explanation above, it makes sense now.

Best regards,

Pavel