OTP mirror register map

[Shivani_Elavena]

Subject: Request for PF5020 OTP Mirror Register Map Documentation

Hi,

We are currently working on communication between the PF5020 PMIC and an NXP controller. During our review of the PF5020 datasheet, we could not find detailed information regarding the OTP mirror register map, including register addresses and pin-level descriptions related to OTP configuration.

The output voltages we need are 1.1v,1.8v and3.3v

Could you please advise if this information is available in a separate document? This is essential for us to correctly interpret and configure the OTP-related settings in our system.

We would appreciate your guidance or any relevant documentation you can share.

Thank you in advance!

Shivani 

[TomasVaverka]

Hi,

Section 16.1 of the PF5020 datasheet provides a complete OTP mirror register map, including:

- Register addresses 
- Configuration fields such as:
   OTP_VSWx for buck output voltages
   OTP_VLDOx for LDO output voltages
   OTP_SWx_SEQ for power-up sequencing
   OTP_SWx_PDGRP for power-down grouping
   OTP_SWxILIM for current limit settings
   OTP_SWxUV_TH and OTP_SWxOV_TH for UV/OV thresholds

The VDDOTP pin determines whether the device loads configuration from:

- OTP fuses (when VDDOTP = GND)
- Hardwired defaults (when VDDOTP = V1P5D)

The TBBEN pin enables Try-Before-Buy (TBB) mode, allowing temporary configuration and testing of OTP settings before committing to fuse programming.

Keep in mind that OTP programming is not allowed in production by the customer. Only NXP or authorized partners (lower volume) should perform this. During development you can use the KITPF502xSKTEVM.

To configure the PF5020 for 1.1V, 1.8V and 3.3V, you would:

- Set OTP_VSWx or OTP_VSWND1 to the appropriate values for 1.1V and 1.8V
- Set OTP_VLDO1 or OTP_VSWND1 to 3.3V, depending on current requirements

These values are programmable in the OTP mirror registers and can be tested in TBB mode before committing.

BRs, Tomas