Hi Sir,
Would you clarify that what is the function of C2& C3 & C5 & C6 on A2I09VD030N reference ?
Is it decoupling cap ? Why needs the value of 3.3uF due to the current is quick low (uA) ?
Because of pules duty (10ms on/off) on Vgs, does it affect of control on PA on/off ? Thanks.
Solved! Go to Solution.
C2,C3,C5, and C6 act as a bypass capacitor. They are used to filter any RF noise that might be on the bias line. Typically the value is quite large to filter noise in the baseband frequency (ie down to 1 MHz). Without such a capacitor the linearity of the device measured as a compliance with a spectral mask may be compromised. However, there is a downside to have such a large charge storage on the gate bias line. The turn on and turn off time of the device will be slowed down with respect to gate blanking (will be longer than 1 uS, in fact could take up to several hundred microseconds), or turning on and off the quiescent current supplied to each of the LDMOS stages.
You must be careful in eliminating all charge storage, on these gate bias lines. These bypass capacitor may also help reduce the low frequency gain bumps. Which if not controlled, might lead to potential instabilities. If the 3.3uF is eliminated, it is suggested that the bypass capacitor which is used is in the range of 200-1000pF at a minimum.
Hope this helps.
C2,C3,C5, and C6 act as a bypass capacitor. They are used to filter any RF noise that might be on the bias line. Typically the value is quite large to filter noise in the baseband frequency (ie down to 1 MHz). Without such a capacitor the linearity of the device measured as a compliance with a spectral mask may be compromised. However, there is a downside to have such a large charge storage on the gate bias line. The turn on and turn off time of the device will be slowed down with respect to gate blanking (will be longer than 1 uS, in fact could take up to several hundred microseconds), or turning on and off the quiescent current supplied to each of the LDMOS stages.
You must be careful in eliminating all charge storage, on these gate bias lines. These bypass capacitor may also help reduce the low frequency gain bumps. Which if not controlled, might lead to potential instabilities. If the 3.3uF is eliminated, it is suggested that the bypass capacitor which is used is in the range of 200-1000pF at a minimum.
Hope this helps.
Thanks a lot.