DDR3, DDR3L, DDR4 have large, wide busses that require management on the PCB routing to optimize their speed of operation. Data busses will have characteristics related to on-die termination and driver strengths for both reads and writes (bidirectional). Address-Command-Control busses will be use the fly-by or serial routing and work unidirectionally. Both require careful selection of driver and receiver characteristics, as well as optimization of the PCB routing and design of the traces on the PCB. This talk will review the driver, receiver, and common PCB characteristics and show how simulation with IBIS models are used to weigh the trade-offs for the DDR bus design.
