Hello Estephania,
I have gone through the hardware user document (UM10858) and the software user manual(UM10913) .we feel that hard power down mode is the best mode for the lowest power consumption.but i have a doubt here.we found its by using the RST_N pin.Any example will be helpful .
How can we put the on PN7462 into hard power mode using the software or just by making the RST_N pin low by giving it to some GPIO.
In document UM10858 section 8.3.5 it's given as below
8.3.5 Hard Power Down Mode
This is the lowest power mode allowing for the highest reduction of the power
consumption. All clocks are turned off, all LDOs are turned off, except the MLDO which is
set to the low power mode
The PN7462 family enters the Hard Power Down mode when RST_N is set to zero or the
VBUS voltage is going below 2.3 V.
The PN7462 family exits the Hard Power Down mode, when RST_N pin is set to high
level and VBUS voltage goes above 2.3 V
But in section 3.3.1.4 in UM10913 (software user manual) it is given as below
RST_N pin behavior
The SecRow contains the bits that control the behavior of HW related to the RST_N pin when pad voltage is not available. Two parameters define the RST_N pin behavior,
RST_N pull-down and RST_N value.
The phhalSysSer_OTP_SecrowConfig() is used to control the RST_N pin behavior.
Table 6. RST_N pin parameters
RST_N pull down RST_N value HW operation
0 X[1] pad voltage availability is always assumed in this system;
IC checks the status of RST_N pin at POR and enters
either HPD or starts ROM booting
1 1 pad voltage availability is not assumed in this system; IC
does not check the status of RST_N Signal and starts
ROM boot normally upon POR
Regards
Sanath
