NTAG5 Link: Single SRAM Block Write Not Triggering I2C Master Read - Full SRAM Write Works

[kavya_ap]

I'm implementing  pass-through application using NTAG5 Link (NTP53x2). The system writes small configuration data blocks to SRAM via NFC and reads them via I2C on an embedded MCU.

Current Findings:

• Single SRAM block write: ED pin does not trigger because it's not the last byte of the 256-byte SRAM

• Full SRAM write: Works reliably - ED pin triggers and I2C master can read the data

• Workaround attempted: Configured ED pin with ED_CONFIG = 1100b (trigger on SYNCH_BLOCK write) and set the target data block as the SYNCH_DATA_BLOCK - still no result.

  Is there a configuration method in NTAG5 Link that allows the ED pin to reliably trigger on a single SRAM block write without requiring the entire SRAM to be written? If not, what is the recommended approach for efficient small-data transfers in pass-through mode?

[EduardoZamora · Accepted solution]

Hello @kavya_ap

Hope you are doing well.

There may not be a direct implementation to trigger ED pin on single SRAM block write. As you mention, pass-through mode expects SRAM write from 00h to 3Fh in order to trigger ED pin, as depicted in NTAG 5 - Bidirectional data exchange, Figure 1.

For proper pass-through implementation, please stick to the procedures and recommendations described in NTAG 5 - Bidirectional data exchange.

Regards,
Eduardo.

[kavya_ap]

Thank you so much.