MFRC530 + LPC2103 via SPI0

[bunny_stew]

Hello,

We have a board with LPC2103 and MFRC530 connected via SPI0. I'm trying to read registers in MFRC530, after reset, but it seems like the received data is wrong. For example: I'm trying to read 8 registers:

• 0x10 (Page);
• 0x11 (TxControl);
• 0x12 (CwConductance);
• 0x13 (PreSet13);
• 0x14 CoderControl;
• 0x15 ModWidth;
• 0x16 PreSet16;
• 0x17 PreSet17.

I have following results:

0x10 - 0x00; 0x11 - 0x00; 0x12 - 0x58; 0x13 - 0x3F; 0x14 - 0x3F; 0x15 - 0x19; 0x16 - 0x13; 0x17 - 0x00.

According to the data sheet, after reset, registers should look like this:

0x10 - 0x80; 0x11 - 0x58; 0x12 - 0x3F; 0x13 - 0x3F; 0x14 - 0x19; 0x15 - 0x13; 0x16 - 0x00; 0x17 - 0x00.

It seems like the result set is right shifted by one. What could be wrong with my setup?

LPC2103 PLL settings:

    //LPC2103 70 MHz MAX!
    //M    = 5
    //P = 2
    //FOSC = 13.56 MHz    BQ1
    //CCLK = M * FOSC ~ 67.8 MHz
    //FCCO = CCLK * 2 * P ~ 280 Mhz
    PLLCON    = 0x01;
    PLLCFG    = 0x24;
    PLLFEED = 0xAA;
    PLLFEED = 0x55;
    while ( !(PLLSTAT & 0x00000400) )
    { ; }
    PLLCON    = 0x03;
    PLLFEED = 0xAA;
    PLLFEED = 0x55;
    APBDIV    = 0x01;

SP0 settings:

    //                          SCK0 P0.4                MISO0 P0.5            MOSI0 P0.6                    SSEL0    P.07
    PINSEL0                |= (1 << (2 * 4)) | (1 << (2 * 5)) | (1 << (2 * 6)) /*| (1 << (2 * 7))*/;
    S0SPCCR                = 0x08;                                        //SPI0 rate = ((5 * 13.56) / APBDIV) / 8 ~ 8.475MHz
    S0SPCR                = 0x20;                                        //master mode, 16-bits per transfer

SPI0 reading function:

uint8_t spi_0_read(uint8_t addr)
{
    uint8_t ret = 0x00;
    FIOCLR    |= (1 << 22);                               //SSEL low
    S0SPDR    = (0x80 | (addr << 1));
    while ( S0SPSR != 0x80 )                          //Wait SPIF         
    { sleep_us(50); }
    ret            = S0SPDR;
    FIOSET    |= (1 << 22);                              //SSEL high
    return ret;
}

Also, I don't quite understand how Page register works. The data sheet says that

The MFRC530 register set is segmented into eight pages contain eight registers each. A
Page register can always be addressed, irrespective of which page is currently selected.

When using the MFRC530 with the dedicated address bus, the microprocessor defines
three address lines using address pins A0, A1 and A2. This enables addressing within a
page. To switch between registers in different pages a paging mechanism needs to be
used.

Table 34. Dedicated address bus: assembling the register address

Register bit: UsePageSelect    Register address
1                                                  PageSelect2 PageSelect1 PageSelect0 A2 A1 A0

LPC2103 P0.4 connected with MFRC530 A2 (SCK0)

LPC2103 P0.5 connected with MFRC530 D0 (MISO0)

LPC2103 P0.6 connected with MFRC530 A0 (MOSIO0)

What should I write into the page register before reading registers of that page? Does the value in 0x81 in the page register means that I've selected the Page 1?

Thanks,

[Kan_Li]

Hi Kim,

I am not the expert for LPC, but for MFRC530 SPI reading, it should be like that:

Please check if you read the data out in the right sequence.

The address byte must meet the following criteria:
• the Most Significant Bit (MSB) of the first byte sets the mode. To read data from the
MFRC530 the MSB is set to logic 1
• bits [6:1] define the address
• the Least Significant Bit (LSB) should be set to logic 0.

The Page register is just for interfacing with Parallel Port, but since you are using SPI communication, it is disabled.

Please also check if the SPI connection is following as it is in the data sheet.

Hope that helps,

Have a great day,
Kan

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[bunny_stew · Accepted solution]

Hello Kan,

I tried to read n bytes and now it works. I just missed n + 1 byte, it must be 0x00. After receiving data on MISO first byte is ignored and I have nice array of requested bytes.

Thanks anyway.