FLEXSPI two channel I deploy an application with imxRT1062 with 2 Flash device. One connected to FLEXSpiA port A1 (is used to code storage and running) and the second to FLEXSpiB port B1 (data storage). I have follow this topic https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/Using-2nd-flexSPI-not-boot-device-to-store-NVM-data/m-p/1284876 and I change this define: #define EXAMPLE_FLEXSPI FLEXSPI2 #define FLASH_SIZE 0x400000 /* 32Mb/4MByte */ #define EXAMPLE_FLEXSPI_AMBA_BASE FlexSPI2_AMBA_BASE #define FLASH_PAGE_SIZE 256 #define EXAMPLE_SECTOR 20 #define SECTOR_SIZE 0x1000 /* 4K */ #define EXAMPLE_FLEXSPI_CLOCK kCLOCK_FlexSpi2 #define FLASH_PORT kFLEXSPI_PortB1 #define EXAMPLE_FLEXSPI_RX_SAMPLE_CLOCK kFLEXSPI_ReadSampleClkLoopbackFromDqsPad I can't read and write data to portB1. I use eaimxrt1062_flexspi_nor_polling_transfer example with this config: Nothing signal (DATA, SCK, CS) active. I've checked the correct pin configuration.  Is it possible use two FLEXSPI at same time? Re: FLEXSPI two channel Hi @Maurizio2 , Thank you so much for your interest in our products and for using our community. Question: Is it possible use two FLEXSPI at same time? Answer: Yes, it is possible. Please refer to the following link,  this application note is highly relevant to your needs. https://www.nxp.com/docs/en/application-note/AN12564.pdf Please carefully check the pin and clock configuration of flexspi, as well as the settings of the LUT table. Wish it helps you. If you still have question about it, please kindly let me know. Best Regards MayLiu

MPC5746Cのフラッシュメモリアレイの整合性チェック こんにちは、 MPC5746C のフラッシュ メモリ アレイの整合性チェックに取り組んでいます。 MPC5746C リファレンス マニュアルに記載されている手順に基づいて関数を作成しました。この機能を実行すると、継続的なリセットが行われます。 手順に基づいて、以下のコードが記述されます。そして、while ループ内で継続的にリセットを行っています。しかし、ブレークポイントを維持し、ステップごとに実行すれば、動作します。 一度ご確認いただき、フィードバックや解決策をご提供いただけますでしょうか。 静的void WaitForAIDBitSet(uint32_t タイムアウト) { 揮発性 int 遅延; (遅延 = 0; 遅延 < 1000; 遅延++) の場合 { __asm__ volatile ("nop"); } while ((C55FMC.UT0.B.AID == 0) && (タイムアウト > 0U)) { タイムアウト - ; } } uint8 フラッシュメモリ整合性テスト(void) { uint32_t misr_result[10]; /* ウォッチドッグを無効にする */ Wdg_modeSwitchInt(FALSE); /* ステップ 1: UTest モードに入る */ C55FMC_UT0 = 0xF9F99999; /* ステップ2: ECC設定 - ECCエラー報告を無効にする */ C55FMC.MCR.B.EER = 0; // ECCイベント情報 C55FMC.MCR.B.SBC = 0; // シングルビット訂正 /* ステップ3: PFLASHの読み取り動作を構成する */ PFLASH.PFCR1.B.RWSC = 0x04; // 待機状態 PFLASH.PFCR1.B.APC = 0x01; // プリフェッチ有効 /* ステップ4: SELx経由でテストするフラッシュブロックを選択する */ C55FMC.SEL0.R = 0x00FF0FFC; C55FMC.SEL1.R = 0x00000000; C55FMC.SEL2.R = 0x00000000; C55FMC.SEL3.R = 0x00000000; /* ステップ5: シーケンシャルアドレッシングを使用する */ C55FMC.UT0.B.AIS = 1; /* ステップ 6: MISR レジスタをシードする */ C55FMC_UM0 = MISR_SEED; C55FMC_UM1 = MISR_SEED; C55FMC_UM2 = MISR_SEED; C55FMC_UM3 = MISR_SEED; C55FMC_UM4 = MISR_SEED; C55FMC_UM5 = MISR_SEED; C55FMC_UM6 = MISR_SEED; C55FMC_UM7 = MISR_SEED; C55FMC_UM8 = MISR_SEED; C55FMC_UM9 = MISR_SEED; /* ステップ7: 配列整合性操作を開始する */ C55FMC.UT0.B.AIE = 1; /* ステップ8: AID = 1（操作完了）を待機します */ WaitForAIDBitSet(0xFFFFFF); // タイムアウト制限を追加する /* ステップ9: MISR値を読み戻す */ misr_result[0] = C55FMC_UM0; misr_result[1] = C55FMC_UM1; misr_result[2] = C55FMC_UM2; misr_result[3] = C55FMC_UM3; misr_result[4] = C55FMC_UM4; misr_result[5] = C55FMC_UM5; misr_result[6] = C55FMC_UM6; misr_result[7] = C55FMC_UM7; misr_result[8] = C55FMC_UM8; misr_result[9] = C55FMC_UM9; /* ステップ10: AIEをクリアする */ C55FMC.UT0.B.AIE = 0; /* ステップ11: 必要に応じてウォッチドッグを有効にする */ Wdg_modeSwitchInt(TRUE); /* ステップ12: MISRの結果を比較する */ if ((misr_result[0] == MISR_UM0) && (misr_result[1] == MISR_UM1) && (misr_result[2] == MISR_UM2) && (misr_result[3] == MISR_UM3) && (misr_result[4] == MISR_UM4) && (misr_result[5] == MISR_UM5) && (misr_result[6] == MISR_UM6) && (misr_result[7] == MISR_UM7) && (misr_result[8] == MISR_UM8) && (misr_result[9] == MISR_UM9)) { FLS_SAFE_STATE_INACTIVE を返します。 } それ以外 { return FLS_SAFE_STATE_ACTIVE; // 整合性チェックに失敗しました } } Re: Flash memory array integrity check on MPC5746C こんにちは、 この関数は、フラッシュ ブロックの実際の MISR 値と output.txt の予想値を比較します。 MISR ツールをセットアップするには、詳細な readme.txt とフォルダーの開始アドレスの例を参照してください。 完全なツールを添付します。Web サンプルでは一部の doc/example ファイルが欠落しているようです。 これで疑問がすべて解消されることを願っています。 よろしくお願いいたします。 ピーター Re: Flash memory array integrity check on MPC5746C ツールがどのようにして期待されるゴールデン署名を計算するのか理解できませんでした。 予想される署名を計算する手順を教えてください。そして、例にあるツールはどのように機能しますか? Re: Flash memory array integrity check on MPC5746C こんにちは、 もう一つの質問があります。計算された MISR 署名値をどのように CAN 検証できるのでしょうか?つまり、取得した署名が正しいかどうかをどのように判断CANのでしょうか? 検証戦略の概要 既知のメモリ領域 (テスト配列など) の MISR シグネチャを計算します。 結果を事前に計算された参照署名 (ゴールデン値) と比較します。 値が一致する場合、メモリの内容は有効であると見なされます。 配列の整合性チェックを完了するために、MISR 署名値を計算して検証するサンプル コードを共有していただけますか? #include "MPC5746C.h" // Replace with actual header for your environment #define ARRAY_SIZE 256 #define CRC_BASE_ADDRESS 0xFF000000 // Replace with actual CRC module base address uint32_t test_array[ARRAY_SIZE] = { /* Fill with known values */ }; uint32_t expected_signature = 0x12345678; // Replace with your golden MISR value void init_crc_module(void) { // Enable CRC module clock // Configure CRC settings (polynomial, seed, etc.) // This is platform-specific and may require register-level access } uint32_t calculate_misr_signature(uint32_t *data, uint32_t size) { volatile uint32_t *crc_data_reg = (uint32_t *)(CRC_BASE_ADDRESS + 0x04); // Data input register volatile uint32_t *crc_result_reg = (uint32_t *)(CRC_BASE_ADDRESS + 0x10); // Result register for (uint32_t i = 0; i < size; i++) { *crc_data_reg = data[i]; } return *crc_result_reg; } int main(void) { init_crc_module(); uint32_t signature = calculate_misr_signature(test_array, ARRAY_SIZE); if (signature == expected_signature) { // Signature matches // Memory integrity is validated } else { // Signature mismatch // Possible memory corruption } return 0; } この例を見てください。これは同じ C55 フラッシュ モジュールのものです。 https://community.nxp.com/t5/MPC5xxx-Knowledge-Base/Example-MPC5744P-FlashArrayIntegrityCheck-test-SSD-GHS614/ta-p/1099524 よろしくお願いいたします。 ピーター Re: Flash memory array integrity check on MPC5746C マシン チェック例外のためリセットが発生しています。 もう一つの質問があります。計算された MISR 署名値をどのように CAN 検証できるのでしょうか?つまり、取得した署名が正しいかどうかをどのように判断 CAN ますか? 配列の整合性チェックを完了するために、MISR 署名値を計算して検証するサンプル コードを共有していただけますか? Re: Flash memory array integrity check on MPC5746C こんにちは、 デバッグ モードではリセットは発生しないため、この問題は何らかのタイマーによって発生していると想定されます。デバッガーによって無効化される SWT と同様。 リセット理由は、RGM [FES/DES] レジスタから読み取ることがCANます。 よろしくお願いいたします。 ピーター

Flash memory array integrity check on MPC5746C Hello,  We are working on checking the flash memory array integrity check on MPC5746C. Based on the steps mentioned in the MPC5746C reference manual we have written the function. When execute this function, continuous reset is happening. Besed on the steps, below code is written. And it is giving continuous reset in while loop. But if I keep breakpoints and go step by step it is working. Could you check once and provide your feedback or solution? static void WaitForAIDBitSet(uint32_t timeout) { volatile int delay; for (delay = 0; delay < 1000; delay++) { __asm__ volatile ("nop"); } while ((C55FMC.UT0.B.AID == 0) && (timeout > 0U)) { timeout--; } } uint8 Flash_Memory_Integrity_Test(void) { uint32_t misr_result[10]; /* Disable watchdog */ Wdg_modeSwitchInt(FALSE); /* Step 1: Enter UTest Mode */ C55FMC_UT0 = 0xF9F99999; /* Step 2: ECC Config - Disable ECC error reporting */ C55FMC.MCR.B.EER = 0; // ECC Event Reporting C55FMC.MCR.B.SBC = 0; // Single Bit Correction /* Step 3: Configure PFLASH read behavior */ PFLASH.PFCR1.B.RWSC = 0x04; // Wait States PFLASH.PFCR1.B.APC = 0x01; // Prefetch Enable /* Step 4: Select flash blocks to test via SELx */ C55FMC.SEL0.R = 0x00FF0FFC;  C55FMC.SEL1.R = 0x00000000; C55FMC.SEL2.R = 0x00000000; C55FMC.SEL3.R = 0x00000000; /* Step 5: Use sequential addressing */ C55FMC.UT0.B.AIS = 1; /* Step 6: Seed the MISR registers */ C55FMC_UM0 = MISR_SEED; C55FMC_UM1 = MISR_SEED; C55FMC_UM2 = MISR_SEED; C55FMC_UM3 = MISR_SEED; C55FMC_UM4 = MISR_SEED; C55FMC_UM5 = MISR_SEED; C55FMC_UM6 = MISR_SEED; C55FMC_UM7 = MISR_SEED; C55FMC_UM8 = MISR_SEED; C55FMC_UM9 = MISR_SEED; /* Step 7: Start Array Integrity Operation */ C55FMC.UT0.B.AIE = 1; /* Step 8: Wait for AID = 1 (operation complete) */ WaitForAIDBitSet(0xFFFFFF); // Add a timeout limit /* Step 9: Read back MISR values */ misr_result[0] = C55FMC_UM0; misr_result[1] = C55FMC_UM1; misr_result[2] = C55FMC_UM2; misr_result[3] = C55FMC_UM3; misr_result[4] = C55FMC_UM4; misr_result[5] = C55FMC_UM5; misr_result[6] = C55FMC_UM6; misr_result[7] = C55FMC_UM7; misr_result[8] = C55FMC_UM8; misr_result[9] = C55FMC_UM9; /* Step 10: Clear AIE */ C55FMC.UT0.B.AIE = 0; /* Step 11: Enable watchdog back if needed */ Wdg_modeSwitchInt(TRUE); /* Step 12: Compare MISR results */ if ((misr_result[0] == MISR_UM0) && (misr_result[1] == MISR_UM1) && (misr_result[2] == MISR_UM2) && (misr_result[3] == MISR_UM3) && (misr_result[4] == MISR_UM4) && (misr_result[5] == MISR_UM5) && (misr_result[6] == MISR_UM6) && (misr_result[7] == MISR_UM7) && (misr_result[8] == MISR_UM8) && (misr_result[9] == MISR_UM9)) { return FLS_SAFE_STATE_INACTIVE; } else { return FLS_SAFE_STATE_ACTIVE; // Integrity check failed } } Re: Flash memory array integrity check on MPC5746C Hello, The function compares the actual MISR values of the flash blocks with the expected values from output.txt. To setup a MISR tool you can refer to detailed readme.txt and folder start address examples. Attached is the complete tool, as it seems that some doc/example files are missing from the one in web example. Hope this will clear all doubts. Best regards, Peter Re: Flash memory array integrity check on MPC5746C We did not understand how the tool works to calculate the expected Golden signature.  Could you please provide the steps to calculate the expected signature. and How the tool present in the example works? Re: Flash memory array integrity check on MPC5746C Hello, I also have another question - how can we validate the calculated MISR signature value? In other words, how can we determine whether the signature we’re getting is correct? Validation Strategy Overview Calculate the MISR signature for a known memory region (e.g., a test array). Compare the result against a precomputed reference signature (golden value). If the values match, the memory content is considered valid. Could you please share sample code that calculates and validates the MISR signature value in order to complete the array integrity checks? #include "MPC5746C.h" // Replace with actual header for your environment #define ARRAY_SIZE 256 #define CRC_BASE_ADDRESS 0xFF000000 // Replace with actual CRC module base address uint32_t test_array[ARRAY_SIZE] = { /* Fill with known values */ }; uint32_t expected_signature = 0x12345678; // Replace with your golden MISR value void init_crc_module(void) { // Enable CRC module clock // Configure CRC settings (polynomial, seed, etc.) // This is platform-specific and may require register-level access } uint32_t calculate_misr_signature(uint32_t *data, uint32_t size) { volatile uint32_t *crc_data_reg = (uint32_t *)(CRC_BASE_ADDRESS + 0x04); // Data input register volatile uint32_t *crc_result_reg = (uint32_t *)(CRC_BASE_ADDRESS + 0x10); // Result register for (uint32_t i = 0; i < size; i++) { *crc_data_reg = data[i]; } return *crc_result_reg; } int main(void) { init_crc_module(); uint32_t signature = calculate_misr_signature(test_array, ARRAY_SIZE); if (signature == expected_signature) { // Signature matches // Memory integrity is validated } else { // Signature mismatch // Possible memory corruption } return 0; } You can have a look at this example, it is for same C55 flash module. https://community.nxp.com/t5/MPC5xxx-Knowledge-Base/Example-MPC5744P-FlashArrayIntegrityCheck-test-SSD-GHS614/ta-p/1099524 Best regards, Peter Re: Flash memory array integrity check on MPC5746C The reset is occurring because of a Machine Check Exception. I also have another question - how can we validate the calculated MISR signature value? In other words, how can we determine whether the signature we’re getting is correct? Could you please share sample code that calculates and validates the MISR signature value in order to complete the array integrity checks? Re: Flash memory array integrity check on MPC5746C Hello, Since reset is not happening when you are in debug mode, I would assume that issue is caused by some timer. Like SWT which is disabled by debuggers. You can read reset reason from the RGM [FES/DES] registers. Best regards, Peter

Feasibility of Upgrading from Nanbield to Scarthgap Yocto for Production – i.MX8QXP Hi NXP Team, We are currently working with the i.MX8QXP platform (imx8qxpc0mek) and have our Yocto setup based on the Nanbield release. As part of our roadmap planning, we would like to understand the feasibility of upgrading to the latest LTS Yocto release Scarthgap  for production use. Could you kindly confirm: Whether Scarthgap is recommended and stable for production builds on the i.MX8QXP? Are there any known compatibility issues or feature gaps (e.g., with modules like display, BT,WiFi, USB-PD, GNSS, eSIM, IMU, power management, STR, etc.) that we should be aware of compared to Nanbield? Do you foresee any migration concerns regarding SCFW porting, Linux BSP layers, or peripheral validation? Is SCFW support and NXP maintained layers (e.g., meta-freescale, meta-imx, meta-nxp-qt6-layer, etc.) already updated for Scarthgap for this SoC? Your input will help us assess the effort required for a potential LTS upgrade and ensure compatibility with our ongoing peripheral and thermal validation plans. Re: Feasibility of Upgrading from Nanbield to Scarthgap Yocto for Production – i.MX8QXP Hello, A1. Yes Scarthgap is LTS on NXP and yocto, You can find it on  6.6.52 BSP: https://www.nxp.com/design/design-center/software/embedded-software/i-mx-software/embedded-linux-for-i-mx-applications-processors:IMXLINUX A2. NXP does not support Nanbield. is not LTS A3. Yes. A4. For Scarthgap yes. Regards

reduced Tx network throughput speeds when writing large files over NFS When running  iperf3 -s over the 10Gbase-t ethernet interface (using TQMLS1046A devkit) the benchmark shows 7.34 Gbaud (Giga bits per second) when the devkit sends (Tx) large data files (note that network path between the two systems is configured  with an MTU size of 9000 bytes for Jumbo frame). When TQMLS1046A is setup to receive the same workload (large files over NFS) on the Rx path of the ethernet interface we get the following error: [ 1068.551554] fsl_dpaa_mac 1af2000.ethernet enet_exp: Err FD status = 0x00080000 My interpretation of this might be misconfiguration of the FSL DPAA ethernet drivers in the kernel config but I don't know where to start. Re: reduced Tx network throughput speeds when writing large files over NFS Testing the changes and will provide an update on whether this is sufficient to resolve our issue. Re: reduced Tx network throughput speeds when writing large files over NFS Please configure the following option in Linux Kernel configuration file. FSL_DPAA_ETH_JUMBO_FRAME - "Optimize for jumbo frames" Optimizes the DPAA1 Ethernet driver throughput for large frames termination traffic (For example, 4K and above). Using this option in combination with small frames increases significantly the driver's memory footprint and may even deplete the system memory. Also, the skb truesize is altered and messages from the stack that warn against this are bypassed.

I²C接続状態に応じたPCA9539リセットの問題 こんにちは、 PCA9539 I/O エクスパンダーを使用していますが、I2C 接続状態に依存すると思われる予期しないリセット問題が発生しました。 問題は次のとおりです。 I²C 通信を介して PCA9539 のすべての出力ポートを HIGH に設定します。 出力ピンは予想どおり HIGH のままです。 ただし、SDA/SCL プローブ (I2C バスの監視に使用) を取り外すと、PCA9539 はリセットされ、出力ピンがデフォルト状態に戻ります。 このプロセス中、VCC は安定したまま継続的に供給され、RESET ピンはプルアップ抵抗を介して HIGH に保持されます。 MCUからの意図的なリセット信号や電源サイクルはありません 追加メモ: 同一のテスト条件下では、この問題は PCA9538 では発生しません。 I2C プルアップ抵抗が存在します。 電源は安定しており、コンデンサで分離されています。 イベント中、RESET ピンは異常なアクティビティを示しません。 プローブを切断する際のグリッチまたは不完全な START/STOP 条件により、PCA9539 の内部 I2C ステート マシンが障害状態になり、リセットのような動作が発生する可能性があると思われます。ただし、明示的なリセットや電源サイクルなしで PCA9539 が出力レジスタをクリアできるかどうかを確認するドキュメントは見つかりませんでした。 私の知る限り、I2C I/O エクスパンダーのCASE、電源が供給されている限り、I2C プローブがコネクテッドされているかどうかに関係なく、構成が保持されるはずです。この理解が正しいかどうか確認していただけますか? 質問: PCA9539 が RESET ピンのアサーションや電源サイクルを行わずに出力レジスタまたは I2C ロジックをリセットできる条件はありますか? プローブの取り外し中に SDA/SCL にグリッチが発生すると、デバイスが障害状態になり、構成された出力が失われる可能性がありますか? 機能が似ているにもかかわらず、なぜこの動作は PCA9539 では発生し、PCA9538 では発生しないのでしょうか? I²C バス接続に関係なく、電源が供給されている限り、I2C I/O エクスパンダーはその構成を維持するというのは正しいですか? この動作に関する洞察や公式ドキュメントがあれば、大変助かります。 よろしくお願いします。

32DS3.4安装问题 安装过程中装S32K3xx development package是遇到问题，见图片 Re: 32DS3.4安装问题 我这边安装SW32K3_RTD_4.4_R21-11_3.0.0_D2303_DS_updatesite实时驱动 现在编译没有问题了 Re: 32DS3.4安装问题 请问是已经安装完S32K3 RTD 3.0.0了？ 有没有根据工程里那个description.txt描述的Update Code? Before running the example a configuration needs to be generated. First go to Project Explorer View in S32 DS and select the current project. Select the "S32 Configuration Tool" menu then click on the desired configuration tool (Pins, Cocks, Peripherals etc...). Clicking on any one of those will generate all the components. Make the desired changes(if any) then click on the menu "ConfigTools->Update Code". Re: 32DS3.4安装问题 你好 我就在你给我的这里有一些FAE做的RTD3.0.0的示例 All Example S32K312 DS3.5 RTD-3.0.0下载了个S32K312_UART_DMA的程序后  辨析报错了如下图 Re: 32DS3.4安装问题 从S32K3 RTD 2.0.3之后，RTD就没有再包含S32K312的demo了。  网上能找到一些S32K312的示例，但都不像S32K344那样包含各个外设模块。 这里有一些FAE做的RTD3.0.0的示例 All Example S32K312 DS3.5 RTD-3.0.0 请问你按照我之前给你的链接，还能下载到RTD2.0.x吗？“Previous” tab里也找一下。 Re: 32DS3.4安装问题 你好 我这边S32DS3.6.3安装好了 我这边买的S32K312MINI-EVB开发板 请问官网的demo程序在哪块找？ Re: 32DS3.4安装问题 好的 我装一个新的版本试试 Re: 32DS3.4安装问题 Hi 抱歉 我看你之前是想要在S32DS v3.6.1里安装S32K3 RTD 2.0.x。 但如果你以前没下载过旧版本RTD的话，可能现在只能看到几个更新版本的RTD了。 点击 S32K3 Standard Software -> Automotive SW - S32K3/S32M27x - Real-Time Drivers for Cortex-M S32DS v3.6.x开始安装RTD简化了很多，只需要照着Offline Package Installation Setup步骤选择下载好的RTD离线包(_DesignStudio_updatesite.zip)就行了。 不建议使用S32DSv3.4这么旧的版本，现在的S32DS已经升级到v3.6.3了。 Best Regards, Robin ------------------------------------------------------------------------------- Note: - If this post answers your question, please click the "ACCEPT AS SOLUTION" button. Thank you! - We are following threads for 7 weeks after the last post, later replies are ignored Please open a new thread and refer to the closed one, if you have a related question at a later point in time. -------------------------------------------------------------------------------

i.mx53 快速用户板 我的主板附带的 microSD 卡不好。在哪里可以下载最新的 iso Linux 镜像，该镜像将使用此快速入门板启动？ 评估板 Re: i.MX53 Quick User Board 您好， 请参考此文档进行版本。 https://www.nxp.com/webapp/Download?colCode=IMX53_1109_LINUXDOCS_BUNDLE &location=null& fsrch=1 &sr=1 &Parent_nodeId=from%20search&Parent_pageType=from% 20search& Parent_nodeId=from%20search&Parent_pageType=from% 20search Best Regards, Zhiming

MBDTで生成されたコードをMatlabからS32DSにエクスポートする Matlab v2021b で MBDT を使用してコードを生成しました。ただし、組み込みコーダを使用してコードを生成した後、projectinfo.xml ファイルを s32DS にインポートしようとしました。しかし、エラーを下回っています。 S32DS V3.5を使用しています。S32DSのバージョンを変更してみる必要がありますか? 誰か、これを手伝ってください。 よろしくお願いします。 ロヒット Re: Export MBDT generated code from Matlab to S32DS こんにちは、 @rohit1749さん Simulink モデルのビルド プロセスとそれに続くコード生成に続いて、次の手順では modelName_Config フォルダーを S32 Design Studio (S32DS) にインポートします。 ファイル -> インポートを押してください 一般 -> 既存のプロジェクトをワークスペースへ -> 参照 -> modelName_Config フォルダを選択 その後、S32DS でアプリケーションをビルドおよびデバッグできるようになります。 進捗状況をお知らせください。 よろしくお願いいたします。 ドラゴス

Issue with sw1 regulator Hi, I hope this message finds you well. We are currently working with the PF5020 in (TBB) mode SW1 regulator, and we have encountered an issue. While writing to the SW1 RUN VOLT register, the values do not appear to be reflected on the SW1LX pin as expected. Could you please provide guidance on why this might be happening or suggest any troubleshooting steps we should follow to resolve this issue? And please provide sw1 regulator configuration sequence. Best regards, [Shivani] Re: Issue with sw1 regulator If you want to operate TBB mode please use our recommend socket board or EVB and use the special timing to enter into TBB mode then update the registers. PF502x Programming Board | NXP Semiconductors For more detail  you can read  attached file from page21--- 7.2 Operating in TBB mode

WDOG32 Interrupt Not Triggering Before Reset on i.MX8ULP Hello, I am working on the i.MX8ULP  and trying to use the WDOG32 in interrupt mode before it triggers a reset. Even though I have configured the watchdog with interrupt enabled, it is still behaving as a normal watchdog — it resets the system directly without generating an interrupt. void WDOG0_IRQHandler(void) { PRINTF("Watchdog IRQ triggered! Count = %u\r\n", wdog_irq_count); /* Clear interrupt flag */ WDOG32_ClearStatusFlags(WDOG0, kWDOG32_InterruptFlag); wdog_irq_count++; SDK_ISR_EXIT_BARRIER; } /* Get default configuration */ WDOG32_GetDefaultConfig(&config); /* Enable interrupt mode */ config.enableInterrupt = true; config.timeoutValue = WDOG_TIMEOUT_VALUE; NVIC_EnableIRQ(WDOG0_IRQn); for (temp = 0; temp < DELAY_TIME; temp++) { __NOP(); } /* Initialize WDOG32 with config */ WDOG32_Init(WDOG0, &config); while(1) { } I have attached full wdog32.c file also in that watchdog IRQ i have put watchdog refresh but still it is resetting after timeout occurs. Are there any additional initialization needed for WDOG32 interrupt mode and in this i only required interrupt not reset is it possible? i.MX8ULP Re: WDOG32 on ARBB mode of cortex-M33 after reset bootup issue on i.MX8ULP Hi, @Bio_TICFSL  Have you checked with the EVK to bootup on 0.9V when watchdog is resetting?  Re: WDOG32 on ARBB mode of cortex-M33 after reset bootup issue on i.MX8ULP Hi, @Bio_TICFSL  I have tested with the EVK using the watchdog example code at the default high frequency, and it boots fine. However, when I lower the voltage to 0.9V  (as in my earlier code snippet), after a watchdog timeout occurs the core gets stuck during bootup. If you have tested this on the EVK at 0.9V. Could you please share the exact code/configuration that you used on the EVK for this test? Regards, Re: WDOG32 on ARBB mode of cortex-M33 after reset bootup issue on i.MX8ULP Hi, The code is fine I just looking something that decrease the voltage, because  ~9.0 volts boot ok with the EVK. Regards Re: WDOG32 on ARBB mode of cortex-M33 after reset bootup issue on i.MX8ULP Hii, @Bio_TICFSL  status = UPOWER_ChngRTDDomBias(DRIVE_MODE_UD); assert(status == 0); status = UPOWER_ChngPmicVoltage(PMIC_BUCK2, PMIC_VOLTAGE_0_9V); if (status == 0) { status = UPOWER_GetPmicVoltage(PMIC_BUCK2, &voltage); if (status == 0 && voltage == PMIC_VOLTAGE_0_9V) { // success } else { assert(false); } } else { assert(false); } During debugging I found that: When the PMIC is set to 0.9V in ARBB mode, after a watchdog reset the core gets stuck during boot. If I increase the PMIC voltage to 1.0V or 1.1V, the reset and boot work fine, even at lower frequencies. I need to keep the PMIC voltage at 0.9V to save power, but with this setting the system cannot reliably boot after a watchdog reset. 👉 What might be causing this issue at 0.9V, and are there any recommended changes or workarounds to ensure the core can boot properly after a reset at this voltage? Any help or guidance would be appreciated. Re: WDOG32 on ARBB mode of cortex-M33 after reset bootup issue on i.MX8ULP On the Cortex-M33 of the i.MX8ULP, I have configured the M33 core to run in ARBB mode. When the watchdog timeout occurs, it tries to reset the core. However, during the reboot process the core seems to get stuck, because before the reset the code had switched the M33 into ARBB mode, which runs at a lower frequency. What modifications are required so that if the core is running in ARBB mode and a watchdog reset occurs, it can successfully boot up again? Re: WDOG32 Interrupt Not Triggering Before Reset on i.MX8ULP Hii, @Bio_TICFSL  I am able to use the watchdog in non-interrupt mode, and it is resetting the system as expected. However, I require the watchdog interrupt mode, and I am not sure about the correct configuration steps for enabling and handling the interrupt. Can you please guide me on how to enable WDOG32 in interrupt mode so that my code actually enters the WDOG32 IRQ handler before reset? Re: WDOG32 Interrupt Not Triggering Before Reset on i.MX8ULP Hello, Yes, it should be possible according to Reference Manual, look at chapter 9.1.7 Power mode details (real-time domain): As you can see all the necessary components to WDOG0 are available during ARBB mode, but maybe there is the possibility that uPower is gating clock of this WDOG or maybe of entire PBRIDGE0. Please take a look to the uPower Firmware User's Guide. Regards

WDOG32 Interrupt Not Triggering Before Reset on i.MX8ULP Hello, I am working on the i.MX8ULP  and trying to use the WDOG32 in interrupt mode before it triggers a reset. Even though I have configured the watchdog with interrupt enabled, it is still behaving as a normal watchdog — it resets the system directly without generating an interrupt. void WDOG0_IRQHandler(void) { PRINTF("Watchdog IRQ triggered! Count = %u\r\n", wdog_irq_count); /* Clear interrupt flag */ WDOG32_ClearStatusFlags(WDOG0, kWDOG32_InterruptFlag); wdog_irq_count++; SDK_ISR_EXIT_BARRIER; } /* Get default configuration */ WDOG32_GetDefaultConfig(&config); /* Enable interrupt mode */ config.enableInterrupt = true; config.timeoutValue = WDOG_TIMEOUT_VALUE; NVIC_EnableIRQ(WDOG0_IRQn); for (temp = 0; temp < DELAY_TIME; temp++) { __NOP(); } /* Initialize WDOG32 with config */ WDOG32_Init(WDOG0, &config); while(1) { } I have attached full wdog32.c file also in that watchdog IRQ i have put watchdog refresh but still it is resetting after timeout occurs. Are there any additional initialization needed for WDOG32 interrupt mode and in this i only required interrupt not reset is it possible? i.MX8ULP Re: WDOG32 on ARBB mode of cortex-M33 after reset bootup issue on i.MX8ULP Hi, @Bio_TICFSL  Have you checked with the EVK to bootup on 0.9V when watchdog is resetting?  Re: WDOG32 on ARBB mode of cortex-M33 after reset bootup issue on i.MX8ULP Hi, @Bio_TICFSL  I have tested with the EVK using the watchdog example code at the default high frequency, and it boots fine. However, when I lower the voltage to 0.9V  (as in my earlier code snippet), after a watchdog timeout occurs the core gets stuck during bootup. If you have tested this on the EVK at 0.9V. Could you please share the exact code/configuration that you used on the EVK for this test? Regards, Re: WDOG32 on ARBB mode of cortex-M33 after reset bootup issue on i.MX8ULP Hi, The code is fine I just looking something that decrease the voltage, because  ~9.0 volts boot ok with the EVK. Regards Re: WDOG32 on ARBB mode of cortex-M33 after reset bootup issue on i.MX8ULP Hii, @Bio_TICFSL  status = UPOWER_ChngRTDDomBias(DRIVE_MODE_UD); assert(status == 0); status = UPOWER_ChngPmicVoltage(PMIC_BUCK2, PMIC_VOLTAGE_0_9V); if (status == 0) { status = UPOWER_GetPmicVoltage(PMIC_BUCK2, &voltage); if (status == 0 && voltage == PMIC_VOLTAGE_0_9V) { // success } else { assert(false); } } else { assert(false); } During debugging I found that: When the PMIC is set to 0.9V in ARBB mode, after a watchdog reset the core gets stuck during boot. If I increase the PMIC voltage to 1.0V or 1.1V, the reset and boot work fine, even at lower frequencies. I need to keep the PMIC voltage at 0.9V to save power, but with this setting the system cannot reliably boot after a watchdog reset. 👉 What might be causing this issue at 0.9V, and are there any recommended changes or workarounds to ensure the core can boot properly after a reset at this voltage? Any help or guidance would be appreciated. Re: WDOG32 on ARBB mode of cortex-M33 after reset bootup issue on i.MX8ULP On the Cortex-M33 of the i.MX8ULP, I have configured the M33 core to run in ARBB mode. When the watchdog timeout occurs, it tries to reset the core. However, during the reboot process the core seems to get stuck, because before the reset the code had switched the M33 into ARBB mode, which runs at a lower frequency. What modifications are required so that if the core is running in ARBB mode and a watchdog reset occurs, it can successfully boot up again? Re: WDOG32 Interrupt Not Triggering Before Reset on i.MX8ULP Hii, @Bio_TICFSL  I am able to use the watchdog in non-interrupt mode, and it is resetting the system as expected. However, I require the watchdog interrupt mode, and I am not sure about the correct configuration steps for enabling and handling the interrupt. Can you please guide me on how to enable WDOG32 in interrupt mode so that my code actually enters the WDOG32 IRQ handler before reset? Re: WDOG32 Interrupt Not Triggering Before Reset on i.MX8ULP Hello, Yes, it should be possible according to Reference Manual, look at chapter 9.1.7 Power mode details (real-time domain): As you can see all the necessary components to WDOG0 are available during ARBB mode, but maybe there is the possibility that uPower is gating clock of this WDOG or maybe of entire PBRIDGE0. Please take a look to the uPower Firmware User's Guide. Regards

MBDT 何时支持 RTD 6.0.0 和 S32DS 3.6？ 我需要使用 S32K3 TCP/IP 协议栈 3.0.0、它基于 RTD 6.0.0 和 S32DS 3.6。 目前，MBDT 的最新版本是 1.6.0、基于 RTD 5.0.0 和 S32DS 3.5。 请问是否计划让 MBDT 支持 RTD 6.0.0 和 S32DS 3.6，这样我就可以在自定义代码中调用 TCP/IP 3.0.0？ 感谢您处理此事。 Re: When will MBDT support RTD 6.0.0 and S32DS 3.6? 你好，@pro778tw、 感谢您对 S32K3 基于模型的设计工具箱的关注。 将在本季度末发布的下一个工具箱版本（ MBDT S32K3 版本 1.7.0）中增加对 RTD 6.0. 0 和 S32DS 3.6 的支持。 顺祝商祺！ 德拉古

GTM Configure Tools license request Hi everyone, I'm trying to apply for a license for the GTM configure tools. When sending the relevant email to complete the process, I encountered a "Delivery incomplete" error from Gmail. The system shows there was a temporary problem delivering the message, and Gmail will retry for 20 more hours. But I'm worried this might affect the license application progress. Has anyone else faced a similar email delivery issue when applying for this license? How did you resolve it? Any suggestions on what I can do to make sure the email gets through successfully would be really appreciated. Thanks in advance!   Re: GTM Configure Tools license request Hello, Try it now. I was able request add GTM SW to your account. You should see it now in your NXP account. Best regards, Peter Re: GTM Configure Tools license request @petervlna  Thank you so much for your quick response and willingness to help resolve my GTM access issue—it’s really appreciated! Best regards Re: GTM Configure Tools license request Hello, Unfortunately admin is out of office and I have no info when he will be back. Could you please rise a request to : [email protected] for adding your account to access for GTM download / license access? Best regards, Peter Re: GTM Configure Tools license request Hello, OK, I will inform you once to access is successfully added. Best regards, Peter Re: GTM Configure Tools license request @petervlna  Thank you for your prompt response and assistance. I would like to request access to the GTM folder for the license using my email account: [email protected]. Please let me know if any further information is needed from my side to complete this process. I appreciate your help in coordinating with the admin to add the necessary permissions. Best regards Re: GTM Configure Tools license request Hello, Looks like you do not have access to the GTM. From what email account you would like to get access to GTM folder for license? I will ask admin to add the right for you. Best regards, Peter Re: GTM Configure Tools license request @petervlna  When I download other software from NXP, the process correctly redirects me to the Product List interface as shown in your previous image. However, when I attempt to download the GTM Configure Tools, it does not redirect to that Product List interface. Instead, it redirects to a different interface (as described below/attached). Thank you for your assistance.   Best regards,   Re: GTM Configure Tools license request Hello, The only reason could be that you do not have access to that SW. You can try manually find it in product list under NXP Software: Best regards, Peter Re: GTM Configure Tools license request  @petervlna  I've already downloaded the GTM configuration tools from the website you mentioned and installed it. But I'm wondering where the license download button you mentioned is. Also, on this interface, there's no display of the license key you referred to, and I can't find it through search either. Do you know what might be causing this? Re: GTM Configure Tools license request Hello, Licenses can be obtained via the https://www.nxp.com/gtmconfigtool website. If you are a new to the website, you will need to create a login account. Both trial and permanent licenses can be generated from there. For a trial license, select the 'Download' button. For the permanent license, select the 'Buy' button. You will be presented with an option to generate a license on the 'License Keys' tab on the Product Download page. Thereafter, you can proceed to 'My Account' and then 'Software Licensing and Support' to maintain your licenses and access updated product downloads. Actually the above statement is not fully true as I had to go via NXP SW account to the GTM to be able to download the license. The online request via GTM tool for license is not working for many years, as the email is sent to freescale email address which no longer exists. Best regards, Peter

I3C Does the LPCXpresso860-MAX development board support the DDR mode of I3C ?

RT1170EV 呼び出し: MCU C++ リンカー arm-none-eabi-c++ -nostartfiles -nodefaultlibs -nostdlib -mcpu=cortex-m7 -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -T evkbmimxrt1170_freertos_generic_cm7_Debug.ld -o "evkbmimxrt1170_freertos_generic_cm7.axf"./xip/dcd.o./xip/evkbmimxrt1170_flexspi_nor_config.o ./xip/fsl_flexspi_nor_boot.o ./xip/xmcd.o ./utilities/str/fsl_str.o ./utilities/debug_console_lite/fsl_debug_console.o ./utilities/fsl_assert.o ./utilities/fsl_memcpy.o ./startup/boot_multicore_slave.o ./startup/startup_mimxrt1176_cm7.o ./source/freertos_generic.o ./source/semihost_hardfault.o ./freertos/freertos-kernel/ポータブル/MemMang/heap_4.o ./freertos/freertos-kernel/ポータブル/GCC/ARM_CM4F/port.o ./freertos/freertos-kernel/croutine.o ./freertos/freertos-kernel/event_groups.o ./freertos/freertos-kernel/list.o ./freertos/freertos-kernel/queue.o ./freertos/freertos-kernel/stream_buffer.o ./freertos/freertos-kernel/tasks.o ./freertos/freertos-kernel/timers.o ./freertos/FreeRTOSAddons/cpp/Source/ccondition_variable.o ./freertos/FreeRTOSAddons/cpp/Source/cevent_groups.o ./freertos/FreeRTOSAddons/cpp/Source/cmem_pool.o ./freertos/FreeRTOSAddons/cpp/Source/cmutex.o ./freertos/FreeRTOSAddons/cpp/Source/cqueue.o ./freertos/FreeRTOSAddons/cpp/Source/cread_write_lock.o ./freertos/FreeRTOSAddons/cpp/Source/csemaphore.o ./freertos/FreeRTOSAddons/cpp/Source/ctasklet.o ./freertos/FreeRTOSAddons/cpp/Source/cthread.o ./freertos/FreeRTOSAddons/cpp/Source/ctickhook.o ./freertos/FreeRTOSAddons/cpp/Source/ctimer.o ./freertos/FreeRTOSAddons/cpp/Source/cworkqueue.o ./freertos/FreeRTOSAddons/c/Source/dlist.o ./freertos/FreeRTOSAddons/c/Source/mem_pool.o ./freertos/FreeRTOSAddons/c/Source/queue_simple.o ./freertos/FreeRTOSAddons/c/Source/read_write_lock.o ./freertos/FreeRTOSAddons/c/Source/slist.o ./freertos/FreeRTOSAddons/c/Source/stack_simple.o ./freertos/FreeRTOSAddons/c/Source/workqueue.o ./freertos/FreeRTOSAddons/c/Source/zero_copy_queue.o ./ドライバ/fsl_anatop_ai.o ./ドライバ/fsl_cache.o ./ドライバ/fsl_clock.o ./ドライバ/fsl_common.o ./ドライバ/fsl_common_arm.o ./ドライバ/fsl_dcdc.o ./ドライバ/fsl_gpc.o ./ドライバ/fsl_gpio.o ./ドライバ/fsl_lpuart.o ./ドライバ/fsl_mu.o ./ドライバ/fsl_pgmc.o ./ドライバ/fsl_pmu.o ./ドライバ/fsl_soc_src.o ./device/system_MIMXRT1176_cm7.o ./component/uart/fsl_adapter_lpuart.o ./board/board.o ./board/clock_config.o ./board/hardware_init.o ./board/pin_mux.o D:/nxp/MCUXpressoIDE_25.6.136/ide/plugins/com.nxp.mcuxpresso.tools.win32_25.6.0.202501151204/tools/bin/../lib/gcc/Arm-none-eabi/14.2.1/../../../../Arm-none-eabi/bin/ld.exe: 警告: evkbmimxrt1170_freertos_generic_cm7.axf には RWX 権限を持つ LOAD セグメントがあります D:/nxp/MCUXpressoIDE_25.6.136/ide/plugins/com.nxp.mcuxpresso.tools.win32_25.6.0.202501151204/tools/bin/../lib/gcc/Arm-none-eabi/14.2.1/../../../../Arm-none-eabi/bin/ld.exe: ./xip/fsl_flexspi_nor_boot.o:(.boot_hdr.ivt+0x10):undefined reference to `__boot_hdr_boot_data_loadaddr__' D:/nxp/MCUXpressoIDE_25.6.136/ide/plugins/com.nxp.mcuxpresso.tools.win32_25.6.0.202501151204/tools/bin/../lib/gcc/Arm-none-eabi/14.2.1/../../../../Arm-none-eabi/bin/ld.exe: ./xip/fsl_flexspi_nor_boot.o:(.boot_hdr.ivt+0x14): `__boot_hdr_ivt_loadaddr__' への未定義の参照 collect2.exe:エラー: ld は 1 の終了ステータスを返しました メイク[1]: *** [メイクファイル:82: evkbmimxrt1170_freertos_generic_cm7.axf]エラー1 make: *** [makefile:73: all] エラー 2 「make -r -j8 all」は終了コード 2 で終了しました。ビルドが不完全である可能性があります。 ===================================================== 「アプリケーションを RAM にリンク」を選択すると、上記のエラーが発生します。選択されていない場合はエラーは報告されません Re: RT1170EV こんにちは@yanpingzhuさん 追加情報をありがとうございます。これは、C ファイルと CPP ファイルを管理するための IDEs のリンク スクリプトの違いによるものと思われます。次の 2 つのマクロ定義は手動で変更する必要があります。これはコンパイルされて成功します。 よろしくお願いします、 ギャビン Re: RT1170EV ご回答ありがとうございます Cコンパイラを使用して「アプリケーションをRAMにリンク」を選択した場合にはエラーは発生しません。C++コンパイラを使用して「アプリケーションをRAMにリンク」を選択した場合にのみエラーが発生します。 Re: RT1170EV こんにちは@yanpingzhuさん NXP MIMXRTシリーズにご興味をお持ちいただきありがとうございます。 提供されたエラー メッセージから、問題はリンク スクリプト内の `__boot_hdr_ivt_loadaddr __' and `__ boot_hdr_boot_data_loadaddr__' によって発生しているようです。 ただし、Link-to-RAM は XIP イメージを生成しないため、IDEs の車載生成スクリプトは異なり、boot_hdr セクションが含まれません。したがって、「リンカー スクリプトの管理」がチェックされていることを確認し、クリーンアップしてから再度コンパイルしてください。

[S32K388] BIST Prerequisite Details Clarifications Hi Team, Customer is looking for some clarifications about information updated in latest version of the SAF/SPD Bist User Manual: Looking into the newer version SAF BIST documentation, this is now the wording mentioned: 1) Is this an incorrect statement for the S32K388 device. Reading this as stated, it seems to imply that for the S32K388 it is recommended to run the BIST on CM7_0 core. This seems to be in stark contrast with what your device safety manual is suggesting that all safety checks should be running on the master safety core (AOU_SW_SAFETY_CORE_USAGE), and the master safety core is defined as CM7_2 core on the S32K388. 2) Can you address the below questions for clarification: Is it mandatory that the cores that the BIST is NOT executing on are "disabled", or just a recommendation?  Does "disabled" here mean the cores are literally halted in hardware and are not at all executing, or if they are simply in a software wait loop with all interrupts disabled and waiting for the BIST to be completed good enough?  If it really needs to be halted in hardware, does this effectively exclude the option for me to enable those cores to start automatically through the IVT boot configuration word, and instead have to keep those cores off until after the BIST has executed (and I'd have to develop a software strategy for manually starting the other cores)? Thanks, Daniel V. Safety_SW Re: [S32K388] BIST Prerequisite Details Clarifications Hello Daniel, customer is right about what is master safety core on K388, it will be fixed in BIST UM. As per Safety architects, it doesn't necessarily mean it must be CM7_2, if customer wants to run ASIL_D on CM7_0, and has K388_LS chip variant it is possible to consider CM7_0 as master safety core and run SAF from that core. Second question is HW related, but simple answer is to keep the other cores in reset, which should be default state. Typically which cores are enabled is set in startup in Boot Configuration Word as customer mentioned, so yes to run online BIST on K3 requires to run the other cores after BIST within customer SW - I think using MCU driver via Mcu_SetMode(). It's a good question whether it should be enough to put the other cores into SleepMode or some loop where it will do nothing, but this use case is not validated - HW team need to confirm. My understanding is that BIST is accessing some HW and Memories which can be used by other cores (check RM e.g. for instruction and data cache blocks covered be MBIST) if there would be some app running so it would corrupt correct BIST execution. Kind Regards, Radoslav

sBoot NCF 测试 - 反应配置 您好， 在目前的配置中，eMcem 模块中的 R1 反应配置了少数 FCCU 故障。 在 sBoot 中配置 FCCU 测试时，无法使用 R1 配置。只有 R1_R2 可用。 为 R1_R2 配置时，预计将启用 NMI，这将导致当前应用程序的 RESET。 如何仅为 sBoot FCCU NCF 测试配置 R1？ SAF 版本：SW32G_SAF_2.0.2_QLP01_D2410 Re: sBoot NCF test - Reaction configurations 你好，@Irshad2225 谢谢你的帖子。 我刚刚检查了 sBoot 的代码。 没有只定义 R1 反应，因此不能将其设置为 R1 对您的不便，我深表歉意。 BR 切宁  

S32k3の外部GPIO割り込みの例 こんにちは、 S32K3X4EVB-Q172のプッシュボタンSW5を使用して、単純な外部GPIO割り込みを実行しようとしています。 私はhttps://community.nxp.com/t5/S32-Design-Studio-Knowledge-Base/SIUL2-external-interrupt-example-project-using-S32K3-RTD-without/ta-p/1552335に従っています。 これはメインファイルです しかし、「 SIUL2_ICU_IP_INSTANCE」が宣言されていないというエラーが発生し、他のエラーも発生します SIUL2 INSTANCEは0に設定されていますが、該当するファイルでは更新されていません 設定で何かが足りないのでしょうか？ S32K3X4EVB-Q172ボードでプッシュボタンとLEDトグルを使用したGPIO割り込みについて、これまたは利用可能な例を誰か助けてくれませんか？ プロジェクト フォルダーは下記に添付されています。RTD 5.0.0 を使用しています。 Re: External GPIO interrupt example in S32k3 こんにちは@AntoZ この HOWTO は RTD バージョン 2.0.0 を使用して実装され、その後のリリースでいくつかの変更が導入されました。その結果、新しいバージョンの手順に従うと、いくつかの矛盾が生じる可能性があります。 予期される構成パラメータの不一致により、Siul2_Icu_Ip_Init() 関数のエラー メッセージが表示されます。関数に渡されたパラメータは予期された名前では存在しません。別の識別子で生成されました。 たとえば、 Siul2_Icu_Ip_0_Config_PB_BOARD_InitPeripheralsを使用する代わりに。以下を使用する必要があります: Siul2_Icu_Ip_0_Config_PB 。この正しい設定はSiul2_Icu_Ip_SA_PBcfg.hにあります。ファイル。 より良い参考のために、Siul2_Icu_Ip_BlinkLed_S32K344 の例を確認することをお勧めします。これは、HOWTO で説明されているものと同じアプリケーションを実装します。この例はRTDパッケージに含まれており、例から新しいプロジェクトを作成するときに簡単にアクセスできます。 BR、ヴェインB

FRDM-MCXA156: FlexPWM not working as intended Hello, I'm trying to use the FlexPWM peripheral of the MCXA156 SoC in a FRDM_MCXA156 devboard using Zephyr but I can't get it to fully work. Whatever I try, the pulse and period seen in the associated output pins do not correspond with the values I am assigning it. I have found a way to reproduce the issue using the blinky_pwm example. Using the reproduction steps below I only get a small pulse of less than 1ms in pin P3_6 (where channel 0 of flexpwm0_pwm0 is linked) whenever the PWM is reconfigured, but nothing in between. AFAIK the example should be setting a 50% duty cycle signal and that is not what I am seeing. It is not a regression; I've tried the same thing on a semi-recent commit 0d46a93 and commit 9f6fdae (Where PWM was implemented for the FRDM_MCXA156 board) and the issue still happens. Steps to reproduce: west init repro cd repro && west update Copy the following overlay file to samples/basic/blinky_pwm/boards/frdm_mcxa156.overlay: #include / { pwmleds { compatible = "pwm-leds"; pwm_led_0: pwm_led_0 { pwms = <&flexpwm0_pwm0 0 PWM_MSEC(1) PWM_POLARITY_NORMAL>; label = "PWM LED 0"; }; }; aliases { pwm-led0 = &pwm_led_0; pwm-0 = &flexpwm0_pwm0; }; }; Then: cd zephyr && west build -b frdm_mcxa156 samples/basic/blinky_pwm west flash See incorrect behavior when probing P3_6. Logs don't show much: [00:00:00.000,069] <dbg> pwm_mcux: pwm_mcux_init: Set prescaler 128, reload mode 2 *** Booting Zephyr OS build v4.2.0-2444-g0d46a934171a *** PWM-based blinky Calibrating for channel 0... [00:00:00.017,179] <err> pwm_mcux: Too long period (750000), adjust pwm prescaler! [00:00:00.025,412] <err> pwm_mcux: Too long period (375000), adjust pwm prescaler! [00:00:00.033,645] <err> pwm_mcux: Too long period (187500), adjust pwm prescaler! [00:00:00.041,879] <err> pwm_mcux: Too long period (93750), adjust pwm prescaler! Done calibrating; maximum/minimum periods 62500000/7812500 nsec Using period 62500000 Using period 31250000 Using period 15625000 Using period 7812500 Using period 15625000 Using period 31250000 ... Attached is the (compressed) ELF final binary I got doing these steps. I hope this is just a mistake on my side. Appreciate any feedback on this matter! Thanks in advance Re: FRDM-MCXA156: FlexPWM not working as intended Hi @aperea-cc, Thanks for the suggestions of documenting this somewhere on the Zephyr driver. I will pass it on to the Zephyr team for their consideration. Re: FRDM-MCXA156: FlexPWM not working as intended Hello, Thank you very much for your response and support. Yesterday I did the same thing (Comparing with the example from the official NXP SDK) and ended up noticing that the FlexPWM peripheral only works if the CPU is active. That would explain why in Zephyr doesn't work, since it sleeps for 4 seconds after every PWM configuration. I don't think there's any elegant solution for this problem in Zephyr, since we'd need the CPU busy if we want the PWM to work, so I'm figuring out if the same behaviour I want can be reproduced using FlexIO instead. From reading the reference manual it seems that FlexPWM is the only non-CPU-related peripheral that exhibits this behavior. It's in the same power management category as the watchdog, cache controller or CPU itself. Maybe this could be documented in the Zephyr driver somewhere; I think it'd save a lot of time to newcomers to the SoC. Re: FRDM-MCXA156: FlexPWM not working as intended Hi @aperea-cc, I imported the blinky_pwm example code from the Zephyr repository and added the overlay that you shared. Indeed, the P3_6 pin outputs small pulses instead of actual PWM signals. After this test, I imported the normal pwm example (without Zephyr) and it worked properly with P3_6. This proves that the issue is not hardware, but rather software related. I will continue investigating whether the issue is on application level or on driver level on the Zephyr example. If you have any further developments, let me know. BR, Edwin.