S32k314 Program Flash P/E cycle Hi Community, whats the assured P/E cycles for program flash of S32k314? from datasheet i could get these numbers.  But the program flash of this MCU is 128KB right? then will it have 100,000 P/E cycles or 1000? It is not shown in the table.  In Davinci configurator MCAL configuration i see it shows 1000, but this is for 1MB and 2MB flash blocks right? which is the Code flash right? Re: S32k314 Program Flash P/E cycle thanks Robin for the information and suggestion. That answers my question Re: S32k314 Program Flash P/E cycle Sorry, I am not familiar with MCAL. The data flash of this MCU have 100,000 P/E cycles. But the program flash is 1MB which have 1000 P/E cycles. I am not sure whether this parameter is for data flash or program flash. In addition, S32K3 RTD 2.0.x is too old. It is recommended to use the latest version such as S32K3 RTD 5.0.0 Re: S32k314 Program Flash P/E cycle Hi Robin, thanks for the reply, we are using MCAL version SW32K3_RTD_4.4_2.0.2. i see this parameter under FLS, flash driver. its actually specified within MCAL/RTD delivery -  i'm not sure if this value is really 'used'.   Re: S32k314 Program Flash P/E cycle Sorry I am not familiar with Davinci configurator, please take a screenshot and tell me under which component I see this information. Also, which version of S32K3 RTD are you using? Re: S32k314 Program Flash P/E cycle Hello Robin, thank you for answering my question. I understand now. Then the value of 1000 specified here (taken over from MCAL) is wrong right? Re: S32k314 Program Flash P/E cycle Hi  The Data Flash Memory is a block of 256 KB but 128 KB is reserved to the HSE and this region is protected by hardware. So it have min 100,000 P/E cycles. Best Regards, Robin ------------------------------------------------------------------------------- Note: - If this post answers your question, please click the "ACCEPT AS SOLUTION" button. Thank you! - We are following threads for 7 weeks after the last post, later replies are ignored Please open a new thread and refer to the closed one, if you have a related question at a later point in time. ------------------------------------------------------------------------------- Re: S32k314 Program Flash P/E cycle sorry i meant Dataflash not program flash

MC32PF1510A6EP Voltage configuration and Power Rails mapping to i.MX6ULL Hello, We are using the PMIC MPN MC32PF1510A6EP with a MCIMX6Y2DVM05AB (i.MX6ULL) part. For this we don't see any reference schematics or documentation that can help us understand which power rail on the PMIC is to be connected to the respective power rails on the processor / peripherals. The only reference is the Example schematic on the datasheet, but that is not applicable to the i.MX6ULL. The EVK schematic is similarly not helpful for this purpose. Please help with any references available for the same and also the voltage configuration and power sequencing for the MC32PF1510A6EP part. PF1550 | PF1510 PMIC for i.MX Power solution Re: MC32PF1510A6EP Voltage configuration and Power Rails mapping to i.MX6ULL guowei, Thanks for the prompt response.  Re: MC32PF1510A6EP Voltage configuration and Power Rails mapping to i.MX6ULL Hi  Here I post the PF1510 A6 power tree detail info: You can see A6 OTP configuration detail! Thanks! BR guowei

FEE_Example_S32K344 does not work, inits with Null_PTR The example from the RTD for FEE_Example_s32k344 does not work as it never initializes due to the MemAcc_init and Fee_init being given Null_PTRs, I have managed to find MemAcc_Config/MemAcc_BOARD_InitPeripherals_Config(for 342) for MemAcc_Init, But i cannot find the Fee_ConfigType define for Fee_Init, am I missing an RTD update or something? Re: FEE_Example_S32K344 does not work, inits with Null_PTR The example actually works if I remove all the example assertions which appear to be reading incorrectly? The functions work if the example asserts are skipped over. Now I am more confused on why the example on 342 does not function. Re: FEE_Example_S32K344 does not work, inits with Null_PTR Any suggestion as to what may be issue of MEMIF_UNINIT? Re: FEE_Example_S32K344 does not work, inits with Null_PTR This is being run on the S32K3X4EVB-T172

i.MX8QM audio mclk not enabled Hello, I have a custom board with i.MX8QM and I'm noticing that the mclk0 output is not enabled.  This worked fine on Linux 5.15, but now that I've upgraded to Linux 6.1 the mclk0 is no longer working.  Please see clock summary below... the frequency of the clock is correct, but it is not enabled.  How do I get the mclk to be enabled? cat /sys/kernel/debug/clk/clk_summary enable prepare protect duty hardware clock count count count rate accuracy phase cycle enable ------------------------------------------------------------------------------------------------------- audio_rec_clk0_clk 0 0 0 24576000 0 0 50000 Y aud_rec_clk0_lpcg_clk 0 0 0 24576000 0 0 50000 ? acm_aud_clk0_sel 0 0 0 24576000 0 0 50000 Y acm_aud_clk1_sel 0 0 0 24576000 0 0 50000 Y acm_mclkout0_sel 0 0 0 24576000 0 0 50000 Y mclkout0_lpcg_clk 0 0 0 24576000 0 0 50000 ? acm_mclkout1_sel 0 0 0 24576000 0 0 50000 Y mclkout1_lpcg_clk 0 0 0 24576000 0 0 50000 ? Device tree: sound_card: sound-card { compatible = "simple-audio-card"; simple-audio-card,name = "PCM3168A"; simple-audio-card,aux-devs = <&>; simple-audio-card,widgets = "Speaker", "Channel1out", "Speaker", "Channel2out", "Speaker", "Channel3out", "Speaker", "Channel4out", "Speaker", "Channel5out", "Speaker", "Channel6out", "Speaker", "Channel7out", "Speaker", "Channel8out", "Microphone", "Channel1in", "Microphone", "Channel2in", "Line", "Channel3in", "Line", "Channel4in", "Microphone", "Channel5in", "Microphone", "Channel6in"; simple-audio-card,routing = "Channel1out", "AOUT1L", "Channel2out", "AOUT1R", "Channel3out", "AOUT2L", "Channel4out", "AOUT2R", "Channel5out", "AOUT3L", "Channel6out", "AOUT3R", "Channel7out", "AOUT4L", "Channel8out", "AOUT4R", "Channel1in", "AIN1L", "Channel2in", "AIN1R", "Channel3in", "AIN2L", "Channel4in", "AIN2R", "Channel5in", "AIN3L", "Channel6in", "AIN3R"; simple-audio-card,dai-link@0 { format = "left_j"; bitclock-master = <&snd_cpu>; frame-master = <&snd_cpu>; mclk-fs = <512>; snd_cpu: cpu { sound-dai = <&sai0>; clocks = <&mclkout0_lpcg 0>; dai-tdm-slot-num = <8>; dai-tdm-slot-width = <32>; }; pcm3168_dac: codec { sound-dai = <&pcm3168a 0>; dai-tdm-slot-num = <8>; dai-tdm-slot-width = <32>; }; }; simple-audio-card,dai-link@2 { format = "left_j"; bitclock-master = <&mic_cpu>; frame-master = <&mic_cpu>; mclk-fs = <512>; mic_cpu: cpu { sound-dai = <&sai0>; clocks = <&mclkout0_lpcg 0>; dai-tdm-slot-num = <8>; dai-tdm-slot-width = <32>; }; pcm3168_adc: codec { sound-dai = <&pcm3168a 1>; dai-tdm-slot-num = <8>; dai-tdm-slot-width = <32>; }; }; }; &sai0 { #sound-dai-cells = <0>; assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, <&sai0_lpcg 0>; assigned-clock-rates = <786432000>, <49152000>, <12288000>, <49152000>; clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sai0>; status = "okay"; }; &i2c0 { #address-cells = <1>; #size-cells = <0>; clock-frequency = <100000>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c0>; status = "okay"; // Audio Codec (8-channel output, 6-channel input) pcm3168a: audio-codec@44 { compatible = "ti,pcm3168a"; reg = <0x44>; reset-gpios = <&lsio_gpio4 24 GPIO_ACTIVE_LOW>; clocks = <&mclkout0_lpcg 0>; clock-names = "scki"; clock-frequency = <24576000>; assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, <&mclkout0_lpcg 0>; assigned-clock-rates = <786432000>, <49152000>, <24576000>, <49152000>; #sound-dai-cells = <1>; VDD1-supply = <&reg_3v3>; VDD2-supply = <&reg_3v3>; VCCAD1-supply = <&reg_5v0>; VCCAD2-supply = <&reg_5v0>; VCCDA1-supply = <&reg_5v0>; VCCDA2-supply = <&reg_5v0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_codec_clk &pinctrl_audio_reset>; }; }; pinctrl_codec_clk: codec_clk { fsl,pins = < IMX8QM_MCLK_OUT0_AUD_ACM_MCLK_OUT0 0xc0000020 >; }; Re: i.MX8QM audio mclk not enabled I figured out the problem.  In the audio amplifier node I had an incorrect setting in the 6.1 kernel which caused this to not work.  Strange that there wasn't an error in the dmesg, but after fixing this incorrect configuration the mclk started working.  Thank you for your help! Re: i.MX8QM audio mclk not enabled Hi @joanxie, Here is the output of the clock and dmesg from 5.15: root@neuralplex:~# cat /sys/kernel/debug/clk/clk_summary enable prepare protect duty hardware clock count count count rate accuracy phase cycle enable ------------------------------------------------------------------------------------------------------- audio_rec_clk0_clk 1 1 0 24576000 0 0 50000 Y aud_rec_clk0_lpcg_clk 1 1 0 24576000 0 0 50000 ? acm_aud_clk0_sel 0 0 0 24576000 0 0 50000 Y acm_aud_clk1_sel 0 0 0 24576000 0 0 50000 Y acm_mclkout0_sel 1 1 0 24576000 0 0 50000 Y mclkout0_lpcg_clk 1 1 0 24576000 0 0 50000 ? acm_mclkout1_sel 0 0 0 24576000 0 0 50000 Y mclkout1_lpcg_clk 0 0 0 24576000 0 0 50000 ? Re: i.MX8QM audio mclk not enabled thanks for your information, do you mind sharing the dump clock and logfile for 5.15 bsp? let me double check it? Re: i.MX8QM audio mclk not enabled Hi @joanxie, That's correct.  The same device tree that works on 5.15 does not work on 6.1.  There are minor changes in the 6.1 device tree due to compatibility (mainly the pcie), but otherwise largely the same device tree.  I've attached the output from dmesg. Re: i.MX8QM audio mclk not enabled the same device tree works on 5.15, but failed on 6.1? do you mind sharing your logfile? 

uint32 startup getAipsRegisterValue(void) and uint32 startup_getControlRegisterValue(void) Where is the definition of startup_getAipsRegisterValue() and startup_getControlRegisterValue()？ When I enabled the MCAL_ENABLE_USER_MODE_SUPPORT definition in the S32K344 code, the compiler reported an error that it could not find the definitions for both functions.   With best wishes Re: uint32 startup getAipsRegisterValue(void) and uint32 startup_getControlRegisterValue(void) Hi @NaYil  Sorry for the delay. Due to workload, my response might be delayed. The MCAL_ENABLE_USER_MODE_SUPPORT macro must be added to the project properties under C/C++ Build > Settings > Standard S32DS C Compiler > Preprocessor and Standard S32DS Assembler > Preprocessor.  Let me know if this works for you.  BR, VaneB

Tabviewはソフトウェアでタブを0に設定できません タイトルの通り、タブビューを使用してスライディング ウィンドウを作成する場合、タブの高さを 0 に設定する必要がありますが、ガイド ソフトウェアの最小設定は 1 です。 Re: Tabview はソフトウェアでタブを 0 に設定できません ありがとう Re: Tabview はソフトウェアでタブを 0 に設定できません こんにちは、張さん。ご返信ありがとうございます。ご回答は承知しておりますが、Guiderで直接設定したいと思っています。そうすれば、チップにダウンロードするのではなく、シミュレータで直接実行できるので、効果の確認に便利です。設定できない場合は、他のコントロールの位置にも影響してしまいます。後から、このタブに吸着されている他のコントロールの位置を手動で調整する必要があり、移植の作業負荷が増大します。

Why CMU should run on a different clock than WDOG? Why CMU should run on a different clock than WDOG? The chip I use is S32K1xx. This is what the Reference Manual says: Re: Why CMU should run on a different clock than WDOG? Got it. Thank you. Re: Why CMU should run on a different clock than WDOG? Hi, the reason is simple: if clock of CMU fails, the watchdog resets application (because is running on another clock) - assuming that CMU's reset is the safe state. Next actions depend on supervisor system. If CMU and watchdog share the same clock, the application got stuck during clock malfunction. Best regards, Pavel

S32K312 Flexcan CANFD mode setting CAN filter problem Excuse me: S32K312 Flexcan CANFD mode to set the CAN filter function FlexCAN_Ip_ConfigRxMb(INST_FLEXCAN_0, RX_MB_IDX_0, &rx_info, 0x55) With this setting, can only the message with ID 0x55 be received? If this function is used to set the filter, how can we receive multiple specific messages (such as ID=0x35, ID=0x68, ID=0x123)? Thanks! Re: S32K312 Flexcan CANFD模式下 设置 CAN filter问题 Hi@Bert2023 "FlexCAN_Ip_ConfigRxMb(INST_FLEXCAN_0, RX_MB_IDX_0, &rx_info, 0x55)"这个函数并不设置filiter,如果你没有设置过filiter，那么默认是每个MB对设置的ID进行所有的比对。 简单来讲，如果你需要设置ID=0x35，ID=0x68，ID=0x123的接收报文，且默认不配置mask,那么你需要为每个ID设置一个MB： FlexCAN_Ip_ConfigRxMb(INST_FLEXCAN_0, RX_MB_IDX_0, &rx_info, 0x35)； FlexCAN_Ip_ConfigRxMb(INST_FLEXCAN_0, RX_MB_IDX_1, &rx_info, 0x68)； FlexCAN_Ip_ConfigRxMb(INST_FLEXCAN_0, RX_MB_IDX_2, &rx_info, 0x123)；

Runtime error 216 at 564BA7AE Dear NXP, I am using MBDT 1.4.0 and NXP S32K312EVB-Q172. Previously, everything worked fine for programming, but suddenly I am unable to perform any actions with the development board. I am using the example "s32k3xx_dio_s32ct" and have confirmed that the hardware is configured as s32k312-Q172. I also verified that the 12V power supply is connected and the OpenSDA driver is functioning correctly. However, I am encountering an error message as shown in the image, and the programming process is interrupted. What could be the cause of this issue? How can I resolve it? Please help me, thanks. MBDT S32K312EVB-Q172  Re: Runtime error 216 at 564BA7AE I resolved the issue by shortening the path of my toolbox. (C:\\Users\\AppData\\Matlab\\Romaining\\Toolbox -> C:\\toolbox) reference: https://community.nxp.com/t5/Model-Based-Design-Toolbox-MBDT/Unable-to-upload-algorithm-on-S32K344-T172-EVB/m-p/1759786/highlight/false#M8671 https://community.nxp.com/t5/Model-Based-Design-Toolbox-MBDT/Programming-S32K344EVB-T172/td-p/1688287

NCJ29D6 Problems after upgrading to new Firmware Hello, After upgrading the board to a new firmware and adapting the application (APP_INFO, new SDK/API), the device remains in HostIF BKP (0x401504 bkpt 0xFF). Flashing the application was initially possible. Debugging (SWD) works, but I get an exception when I try to call NDP functions (debugger only shows ?? for this memory). Re-flashing with Lauterbach script is now also not possible (the memory for the flash driver also shows ??). But I can still attach and debug the currently flashed application. My guess is that the new application cannot be found and the device has now activated SWUP? I'm not quite sure why flashing the new application didn't work and how I should proceed from here? Best regards, Stefan Re: NCJ29D6 Problems after upgrading to new Firmware Hello, Hope you are doing well. Sorry for the inconvenience this might cause you but as the information of this product it's under NDA (Non-Disclosure Agreement) the information it's not public. For more information about the chip could you please contact one of our distributors available in the Distributor Network|NXP? Or if you have any direct contact, please contact them. Regards, Ricardo

S32G3 BSP41 PFE2 RGMII to RGMII without PHY on the customized board Hi, Our hardware design connects PFE2 RGMII directly to the switch RGMII without a PHY. The PFE2 is configured with rgmii-id, and we have verified the 125MHz TX clock output. I have come across discussions suggesting the use of a common external clock for both sides. Is clock drifting the only concern in this setup? If so, is it possible to configure PFE2 as a clock slave and use the clock output from the switch to synchronize TX and RX? Thanks, XD Re: S32G3 BSP41 PFE2 RGMII to RGMII without PHY on the customized board Hello @XD, I am glad you found the information helpful. Thanks for accepting my answer as a solution. Best regards, Alejandro  Re: S32G3 BSP41 PFE2 RGMII to RGMII without PHY on the customized board Hi @alejandro_e , Thank you again for your help. This information is very helpful. Thanks, XD Re: S32G3 BSP41 PFE2 RGMII to RGMII without PHY on the customized board Hello @XD, I can not access the technical information for the Marvell Switch, however, I see it is relatively similar to the SJA1110, for which you can check the following document: AN13335.pdf, in particular please check section 2.2 RGMII interface in page 8:     Let me know if this information solved your problem.   Re: S32G3 BSP41 PFE2 RGMII to RGMII without PHY on the customized board Hi @alejandro_e , We have a Marvell switch port running in RGMII mode, connected to PFE2 on our hardware. Thanks, XD Re: S32G3 BSP41 PFE2 RGMII to RGMII without PHY on the customized board Hello @XD, To the best of my knowledge the same guidelines should apply to any device connected using RGMII, either a PHY or a switch.  with that said, can you share the RGMII device you are connecting the S32G3 to? So I can check if there could be special considerations. Thanks in advance. Re: S32G3 BSP41 PFE2 RGMII to RGMII without PHY on the customized board Hi @alejandro_e , It's great that you're helping me again—I really appreciate it. The guideline you provided is for an RGMII-to-PHY scenario. Do you have any guidelines for a direct RGMII-to-RGMII connection without a PHY? Thanks, XD Re: S32G3 BSP41 PFE2 RGMII to RGMII without PHY on the customized board Hello @XD, It is good to support you again. About your question, please refer the the S32G3 - Hardware Design Guidelines, in particular please check sections: 10 Communication Peripherals, 10.1.1 RGMII signal routing requirements and 13.3 High-speed routing recommendations. There you should be able to find all the relevant information about RGMII on a HW level. Let me know if you have more questions about this topic.    

S23K312EVB MCUに存在するADCに接続するジャンパーピンを特定するのを手伝ってくれる人はいますか 日時:S23K312EVB どうもありがとうございます！

How to obtain the commutation timing sequence table? Hello all:     I am testing the BLDC using the MCSPTE1 AK144 kit.      When I was reading the AN12435.pdf, I saw the Figure 4 "Six-step switching sequence" of page 5, and please refer to the attached sequence.png file.     I want to know how this switching sequence is obtained? What method can be used to obtain the sequence?     Thanks! Best regards, Fedora Re: How to obtain the commutation timing sequence table? Hello Leo:    Ok, I understand now. I will continue my research. Thanks for your help. Best regards, Fedora Re: How to obtain the commutation timing sequence table? Hi, Thank you so much for your interest in our products and for using our community. You could refer to Figure 2. 3-phase BEMF voltages and phase currents of a BLDC motor from the same app note. On the other hand, Six-step commutation is a very common method for driving a 3-phase star-connected BLDC motor, maybe there are more detailed documentation about this on the web. We usually just describe the basics to implement motor control with our MCUs. Hope it helps you. Have a nice day!

How do RFLevel values change the sensitivity of the RF Level Detector on the PN512? Increasing the RFLevel increases the V~Rx [Vpp] based on the table 155 in the pn512 datasheet. What does that mean in terms of sensitivity for the RF Level Detector? Does raising the V~Rx[Vpp] mean I am increasing sensitivity?  Does increasing RFLevel increase the gain for some kind of amplifier thereby increasing the sensitivity or is it raising some type of threshold thereby decreasing the sensitivity?  Thank you NFC Frontend Solutions Re: How do RFLevel values change the sensitivity of the RF Level Detector on the PN512? Hi, Sensitivity should increase as RF level value goes from 0xF to 0x0. Regards, Eduardo. Re: How do RFLevel values change the sensitivity of the RF Level Detector on the PN512? Thank you for your reply. So as RFLevel increases from 0x00 to 0x0F I am increasing the sensitivity of the RFLevel Detector? Or is it the other way around where the sensitivity of the RFLevel Detector is increasing as RFLevel goes from 0x0F to 0x00. Thank you Re: How do RFLevel values change the sensitivity of the RF Level Detector on the PN512? Hello @user_leo Hope you are doing well. The RF level detector detects the presence of an external RF-field delivered by the antenna to the RX pin. The values listed in Table 155 should correspond to a typical voltage that would be seen at the RX pin. However, the sensitivity itself depends on the antenna configuration and tuning. Lower sensitivities are prone to intrinsic noise in the environment, causing misleading results. To increase the sensitivity of the RF level detector an amplifier can be activated by setting the bit RFLevelAmp, but it would be recommended to use it with upper values. Regards, Eduardo.

S32K312ピンマップまたはピン配置図 コミュニティの皆さん、こんにちは。 s32k312EVB-Q172ボードのピンマップまたはピン配置図はどこにありますか? よろしく Re:S32K312ピンマップまたはピン配置図 また、s32k312EVB-Q172 ボードのピン配置も探しています。リファレンスマニュアルをダウンロードしましたが、S32K312_IOMUX.xlsxファイルがありません。PDFにどのように添付されますか?別のダウンロードURLへのリンクはありますか?

freeRTOS for s32k3 2.0.3 ( s32ds v3.4 ) not install During the time of installation i got error which can not be solve using any way that i tried ,    Re: freeRTOS for s32k3 2.0.3 ( s32ds v3.4 ) not install I got my  files through change into location path .  Re: freeRTOS for s32k3 2.0.3 ( s32ds v3.4 ) not install Hi, Thank you so much for your interest in our products and for using our community. For S32K3 FreeRTOS version 2.0.3 you also need S32 Design Studio IDE v3.4 Update 3. This update include the item you need. You can found it in S32K3 page -> Design Resources -> Software -> S32K3 Standard Software -> Automotive SW - S32K3 - S32 Design Studio -> Previous: Then install it in S32DS -> Help -> Install New Software Hope it helps you. Have a nice day!

IMX8QM DP++ (DisplayPort Dual-Mode) Hi, We've a custom (imx8qm) board with an mDP (mini DisplayPort) connector, and I'd like to connect an external HDMI screen using a passive mDP-HDMI adapter. My understanding is that this should be possible if DP++ (DisplayPort Dual-Mode) is supported. I have a few questions regarding DP++ support on the i.MX8QM: i.MX8QM DP++ Support: Does the i.MX8QM processor itself support DP++? Cadence Firmware DP++ Support: Does the Cadence firmware for the i.MX8QM's DisplayPort controller support DP++? Device Tree Configuration: Are there any necessary device tree (dtb) configurations required to enable and utilize DP++ functionality? If so, could you please provide details on the specific settings? Thank you for your assistance. Re: IMX8QM DP++ (DisplayPort Dual-Mode) Hello, Unfortunately DisplayPort Dual-Mode is not supported in i.MX8QM, you need to look into another adapter. I apologize the inconvenience that this may affect your design. Best regards.

What does it mean HSE_SWT_RST on S32K311!!! Hello all. Where can I found information about HSE_SWT_RST reset? With the following clock configuration: PLL_PHI0_CLK=120MHz CORE_CLK=PLL_PHI0_CLK/1=120MHz AIPS_PLAT_CLK=PLL_PHI0_CLK/2=60MHz AIPS_SLOW_CLK=PLL_PHI0_CLK/4=30MHz HSE_CLK=PLL_PHI0_CLK/1=120MHz DCM_CLK=PLL_PHI0_CLK/4=30MHz at power on I occasionally get the reset HSE_SWT_RST. What is the cause? I probably need to reduce the HSE clock to 60 MHz or change the value of HSE_CLK_MODE_AND_GSKT_CTRL to 10 of the dcf_client_utest_misc client. Where can I find documentation that explains this? Best regards E. Re: What does it mean HSE_SWT_RST on S32K311!!! Hi @enricoantonioli  The HSE_SWT_RST is usually caused by wrong clock configuration. It was found out that it is possible to configure 120MHz HSE_CLK only during reset by DCF record. It cannot be done later by software for some reasons. That means it is necessary to set PLL_ENABLE in BCW (Boot Configuration Word) in IVT, it is necessary to program crystal oscillator configuration flag in UTEST at 0x1B000050 (see section 32.4.3.2 Crystal oscillator configuration flag in the S32K3 RM), it is necessary to program the dcf_client_utest_misc - HSE_CLK_MODE_AND_GSKT_CTRL equal to 10 or 11. Re: What does it mean HSE_SWT_RST on S32K311!!! Hi, Thanks for the precious information, but I still don't understand why in my situation there is a HSE_SWT_RST reset. What is the cause? What's wrong with the HSE? Best regards E. Re: What does it mean HSE_SWT_RST on S32K311!!! Hi @enricoantonioli  What does HSE_SWT_RST mean? It stands for HSE Software Watchdog Timer Reset. Is it a reset due to an internal HSE watchdog or what? The HSE CPU is mainly composed of Arm Cortex-M0+, which one of its essential peripherals is the watchdog.  So yes, it is trigger by HSE SWT as the name implies. Why this reset occurs if no firmware is programmed into the HSE memory? The HSE CPU, even if the HSE firmware is not loaded, is active because it contains the SBAF code. Re: What does it mean HSE_SWT_RST on S32K311!!! HI Vane, first of all, thank you very much for your quick reply. At the moment I have reduced the HSE_CLOCK to 60 MHz because in the HSE there isn't programmed a firmware. I will activate HSE soon. What does HSE_SWT_RST mean? Is it a reset due to an internal HSE watchdog or what? What I don't understand is why this reset occurs if no firmware is programmed into the HSE memory? If I understand correctly, at power on the HSE processor executes the SBAF code and then stops in a WFI. So who triggers the HSE_SWT_RST reset? Best regards E. Re: What does it mean HSE_SWT_RST on S32K311!!! Hi @enricoantonioli  According to the information, it seems that the problem is due to incorrect clock configuration. The HSE_CLK_MODE_AND_GSKT_CTRL (bit 30-29) must be set to 1x if you want to use HSE_CLK equal to 120 MHZ. On the other hand, if HSE_CLK_MODE_AND_GSKT_CTRL was set to 00, it is necessary to change HSE_CLK to 60 MHZ. Refer to S32K3xx_DCF_clients file attached to the S32K3xx Reference Manual.  This must be done by writing to dcf in UTEST memory using Flash controller. You can check the following article, it might be a good reference.  [S32K3] Restrict the debug access with a password when HSE is not used BR,VaneB

3V coin cell backup for imx93 Hello everyone, I would like to know if there is any way to use a 3V Coin Cell battery backup for the NVCC_BBSM_1P8 power rail of the imx93 with the PCA9451A PMIC. As I must keep the RTC and Tampers working once the main supply has been shutted down, a Coin Cell backup is needed. In the "4.1.3 Power architecture" section of the imx93 datasheet there is an image which shows the basic diagram for a backup battery. I wonder if there is a way to connect the 3V CC to the PMIC. In order to achive an uninterrumpted NVCC_BBSM_1P8 (provided by LDO1), I must keep INL1 and VSYS above 2.7V  due to the UVLO feature of the PMIC (which is impossible with a 3V CC). Anyway, a LDO with a CC would be pretty bad in terms of efficiency. Is there any way to use a 3V CC backup alongside the PCA9451A to keep NVCC_BBSM_1P8 power rail on? If no, is a power mux with ideal diodes needed to do a custom switchover between the PMIC's LDO output and a regulated (with a buck converter) 3V coin cell to manage this issue? Best regards, Gorka. Re: 3V coin cell backup for imx93 Hello, As is mentioned in PMIC's datasheet, the suggested option is connect a battery and a regulator in NVCC_BBSM_1P8 power rail to keep this power domain on and switch between the PMIC's LDO and regulated output from coin cell. Best regards.

ISO-26262 ASIL-C compliant PIL testing with S32G-VNP-GLDBOX Hi, it there some ISO 26262 certification of S32G-VNP-GLDBOX used together with Matlab Simulink plugin for PIL testing, and some guidelines to prove the toolchain can be considered as qualified? I mean something like MathWorks have their ICE Certification kit?  Simulink plugin: Model-Based Design Toolbox | NXP Semiconductors Re: ISO-26262 ASIL-C compliant PIL testing with S32G-VNP-GLDBOX Hi @Jan_S,  Thanks for the questions. Unfortunately, we do not have the expertise with the MBDT software to give a support with that you can ask at: Model-Based Design Toolbox (MBDT) community, the Goldbox there is known as HCP.  Regarding to the ISO 26262 you can find the following on the S32G3 Reference Manual:   [Page 3660, S32G3 Reference Manual, Rev. 4, 02/2024] Also, at the Product details of the GoldBox 3 Vehicle Networking Development Platform site you could find the next: