PCA9617波形 该电路与 PCA9600 配合良好，但为了降低成本，我修改了电路板以使用 PCA9617 并检查了波形。 观察时钟波形，没有特别的失真， 所以看起来没有问题，但是在数据波形输出低电平的时候， 我观察到在时钟下降沿被拉高的波形。 我想知道这是否是由于时钟和数据之间的串扰造成的（安装 PCA9600DPZ 时没有问题）， 或者是修改电路板图案（图案切割/电缆焊接）的效果？ 我将非常感激您的意见。

Extension update failled  According to the document which named "Getting Started with MR-CANHUBK344 Evaluation Board", I tried to install about "S32K3 RTD AUTOSAR® 4.4 Version 2.0.0" and "S32K3xx development package Version 3.4.3". But it failed like an upload screenshot.  Also I can't find "FreeRTOS for S32K3 2.0.0" at the extension list. How can install correctly? Re: Extension update failled Please refer to the offline installation and online installation methods mentioned in https://community.nxp.com/t5/S32K/S32K3-Unified-Bootloader-Build-Issue/td-p/1653130 S32K3 Reference Software -> Automotive SW - S32K3 - FreeRTOS -> SW32K3_FreeRTOS_10.4.6_2.0.0_D2204 Re: Extension update failled Reason Details: Operation detailsYour original request has been modified."GNU ARM PEMicro Interface Debugging Support" is already installed, so an update will be performed instead.Software being installed: com.nxp.s32ds.brc.arm.tools.gcc102.feature.feature.group 1.0.0.202109281337 Missing requirement for filter properties ~= $0: com.nxp.s32ds.brc.arm.tools.gcc102.feature.feature.group 1.0.0.202109281337 requires 'org.eclipse.equinox.p2.iu; com.nxp.s32ds.brc.arm.tools.gcc102.feature.feature.jar [1.0.0.202109281337,1.0.0.202109281337]' but it could not be found Re: Extension update failled " Also I can't find "FreeRTOS for S32K3 2.0.0" at the extension list. How can install correctly?" is solved. Re: Extension update failled 2.0.0 is no longer there. I only find 2.0.1 which doesn't work. Can you point to SW32K3_FreeRTOS_10.4.6_2.0.0_D2204?

MC9S12C64 Flash Burner Question MC9S12C64, CW V5.9.0, coding in assembler. I'm trying to write code to erase and burn one sector in Flash but I don't seem to be able to figure it out. I've spent hours studying the MC9S12C128V1 reference manual but there are things that just are not clear to me. I'll start with the basics as I understand them: RAM is from address $0400 to address $0FFF (3Kb). Unpaged Flash is from $4000 to $7FFF (16Kb). The Flash erase sector size is 1024 bytes (512 words) I have less than 1024 bytes of configurable constants in my program. They are placed in Flash but copied to RAM on start up to be used from RAM. I want to be able to change some of these values in RAM and burn them back into Flash without having to erase everything and reload the whole program. I have more than enough room in RAM for all my variables plus the copies of the configurable constants, so RAM size is not an issue. My entire program is not all that large so I can dedicate one sector in Flash to these configurable constants and still have lots of room in the unpaged Flash area for my program. Do the Flash sectors have specific addresses, or can they start and stop at any point within the unpaged Flash area? Could I place my configurable constants in Flash from $4000 to $4400 and start my program from $4500 just to be safe? Any suggestions would be greatly appreciated. Thanks, Robert Re: MC9S12C64 Flash Burner Question Hi Ladislav, I did some more experimenting with DP51`2-FLASH-EW-ASM-CW47 and was eventually able to get it to work with my MC9S12C64. Then I was able to get it to work with the small program I wrote to test the erase and burn routine. Now I am quite confident that I will be able to integrate it into my main program. I can't thank you enough for sending that zip file as well as your explanations. I doubt if I ever could have figured it out on my own Regards, Robert Re: MC9S12C64 Flash Burner Question Well, I'm not getting anywhere with this at all. I had no success with any of the code for the C32. I was able to load the C128-FLASH_ERW_4000-7FFF_+CW47 project into my controller. I changed the derivative to MC9S12C64 and it will run, but I have no idea what it's doing. I disassembled main.C and the assembler makes no sense to me either. Is there a code version of this in assembler so I can see if I can integrate it into my code? I am running with an 8mHz oscillator with a bus speed of 24mHz using the PLL. I do have the divider settings calculated correctly. Regards, Robert Re: MC9S12C64 Flash Burner Question Hi Ladislav, Thank you so much for that detailer response. CW is a very powerful program and I have only just touched on what it can do for debugging. I wasn't aware of the "disassemble" feature, or the refresh Flash either. I'll try those with your examples and see what happens. Now that you have confirmed that the erase sector size is 1024 bytes, it makes things much simpler for me. The default RAM from $0400 to $0FFF is more than adequate for my program variables. I can fit all of my configurable constants, (the ones copy I to RAM at start up so I can modify them in RAM  and burn back to Flash) into one sector. My program can easily fit into either of the near Flash blocks ($4000 to $7FFF or $C000 to $FFFF). I would like to place my program, including your example E/W code into $4000 to $7FFF and my configurable constants into $C000 to $FFFF. Does this sound right? Now, which of your example codes should I use? I don't think I could use the C32-FLASH E_R-ASM because of the 512 byte sector erase size.  I could probably use either C128-FLASH_ERW-4000-7FFF-CW47 or C128-FLASH_ERW_CW47 if I can get them disassembled successfully. What about DP512-FLASH_EW_ASM_CW47? I don't think I need that but could it be used for the 9S12XEP100? Many Thanks, Robert  Re: MC9S12C64 Flash Burner Question Hi, I am a little bit confused. The C in the examples is like flow chart in the form I provide it. Moreover, you can use disassemble function. Mouse right button click at C code. Plus you can compare Figure 19-26. Example Program Command Flow from the data sheet with code. Yu can also use simulator for these MCUs or just load my example int the MCU you have and step it. Important note....Do not visualize in memory window of debugger the flash address which is currently E/W. Why? Because BDM reads it and it is also reading while writing. For tests, it is better to read the written word back to some variable....or you can move memory window up and down. Next good note is to set for flash "refresh memory when halting" in the debugger select correct flash blocks...this is only example and match "refresh memory when halting" Of course it is suitable if you also think about critical section and execution part of the code out of the flash…already described. Few words about memory map. If memories overlap then following priority scheme is valid. (page 127) Highest -  BDM (internal to core) firmware or register space …..... Internal register space …..... RAM memory block …..... EEPROM memory block …..... On-chip FLASH or ROM Lowest - Remaining external space Default value of the RAMHAL bit (INITRM) is 1 so the 4k RAM is mapped to higher part of the RAM block. However, 4kRAM is mappable to 4k block so RAMHAL has no meaning in the case of this MCU. Moreover, INITRM[7..3] is set to 0b00001 the RAM is placed to the 4k block where address 0b00001000 00000000 or 0x0800 belongs. 0000-0FFF    1st 4k block of RAM mapping possibility 1000-1FFF      2nd 4k block of RAM mapping possibility 2000-2FFF    3rd 4k block of RAM mapping possibility 3000-3FFF    4th 4k block of RAM mapping possibility So, by default the RAM is mapped to the space 0000-FFFF which means 0000-0FFF    1st 4k block of RAM mapping possibility If the Registers are mapped 0000~03FF and RAM is mapped 0000~0FFF then addresses: - 0000~03FF – address the registers - 0400~FFFF – address the RAM (1 st kB is overlapped by Regs) Near flash - 4000~7FFF – non paged flash addressable also via paged "far" address 0x3E_(8000~BFFF) - C000~FFFF – non paged flash addressable also via paged "far" address 0x3F_(8000~BFFF) Far flash - 0x3C_(8000~BFFF) - paged flash - 0x3D_(8000~BFFF) - paged flash - 0x3E_(8000~BFFF) - paged flash addressable also via no page "near" address 4000-7FFF - 0x3F_(8000~BFFF) - paged flash addressable also via no page "near" address C000-FFFF If you use default mapping then you have smaller RAM. The flash… data sheet page 18… Memory options: — 64K, 96K, or 128Kbyte Flash EEPROM (erasable in 1024-byte sectors) The word which is written must be in erased status. Cumulative programming is not allowed. So, writing to erased word is not problem anytime, but if you want to rewrite byte you have to erase entire sector and write back what was erased together with modified word. Now it is up to your SW how often you will erase sectors and what approach you will develop because the flash has given number of erase cycles for sector. The examples always erase sector before it is written…just an example. Best regards, Ladislav Re: MC9S12C64 Flash Burner Question Hi Ladislav, Thanks so much for your reply. I am programming in assembler and am not fluent in C, so I find it very difficult to translate any code written in C to assembler. Having said that, I really appreciate the zip file you sent. I'll study that and see if I can make sense of it. Besides the MC9S12C64 reference manual I have a book called " The HCS12/9S12" by Huang. It covers a lot of subjects but his examples of erase/burn are not clear to me. Specific to  HC9S12C64, are the sector sizes 512 bytes (256 words) or are they 1024 bytes? Also, does the erase/burn routine do one byte, or one word at a time? Regards, Robert Re: MC9S12C64 Flash Burner Question Hi, One important note… It is not allowed to be flash block E/W while it is read…also reading instruction is included. Because of this, there are two approaches> 1) Routine in RAM See C code flash.h file in SW-C32-FLASH-E_W-FunctionsInRAM-v1_0-CW47 where the routine in asm is placed into RAM and it is done automatically as variable initialization process in start12.c file. I think dissasseble or principle is clear from the C code. Also DP512 (larger device) example does it in this way and I think it also considers critical section which disables interrupt, then waits for flash and finally returns CCR I-bit to the status before action. It is necessary to avoid flash access while EW and interrupt can also do it. #pragma DATA_SEG DEFAULT static UBYTE WaitForFlash[]={   0xC6, 0x80,                           // LDAB #$80      // command buffer empty = 0  0x7B, 0x01, 0x05,                     // STAB _FSTAT   0xC7,                                 // CLRB           // clear return value   0x1E, 0x01, 0x05, 0x20, 0x05,         // BRSET _FSTAT,#32,*+10  0x1F, 0x01, 0x05, 0x10, 0x03,         // BRCLR _FSTAT,#16,*+8  0xC6, 0x05,                           // LDAB  #5             ;ERR_NOTAVAIL  0x3D,                                 // RTS  0x1F, 0x01, 0x05, 0x40, 0xFB,         // BRCLR _FSTAT,#64,*+0  0x3D                                  // RTS }; Or in the example …  C32 - FLASH E_R_W - ASM -01 it is done to the special RAM space once and then called by JSR   $0800                               ; call flash routine in RAM 2) Routine on stack … requires repeating writing the routine from flash to stack before each EW. In the attached asm file it is done onto stack. (There is also very old answer from past related to the mentioned SW-C32-FLASH-E_W-FunctionsInRAM-v1_0-CW47) So it is up to you which way is more suitable for you. Best regards, Ladislav

如何将 MM9Z1I638 设置为安全模式，我需要帮助，谢谢 我对使用MM9Z1I638打开安全模式有疑问。看了手册，知道了FSEC寄存器是用来打开安全模式的，但是这个寄存器好像不支持直接写，需要通过FLASH编程来写入。写入的地址段为P_FLASH块的0xFF_FE0F字节，支持的最小扇区大小 P_FLASH为512字节。我按照擦除扇区、校验扇区、写入扇区的流程写入字节，但是发现每次擦除扇区之后软件都会运行到非法的地方。检查后发现，这个扇区存储的所有信息都是地址 电池传感器 Re: HOW CAN set MM9Z1I638 to safe mode ,i need help,THANKS 这个是一个流程我建议您看下面的帖子： I have a question about using MM9Z1I638 to open the safe mode - NXP Community Re: HOW CAN set MM9Z1I638 to safe mode ,i need help,THANKS 我看了6.14.5里面的安全字节描述，上面写的是在下一次复位以后，会使用0xFF_FE0F地址的值来初始化FSEC寄存器，我现在的问题是如何对0XFF_FE0F这个地址写入值，我之前用上面描述的方法进行扇区擦除后，值通过单步调试的方法能检测到0XFF_FE0F地址的值进行了更改，但是随后运行，通过调试器的数据分析，软件就跳转到了非法的位置，所以我想问问正常的编写这个地址的流程是怎么样的，谢谢 Re: HOW CAN set MM9Z1I638 to safe mode ,i need help,THANKS Hi SHAOWEN 您说的是security吧？ 如果是的话请仔细阅读datasheet page 403：6.14.5 Security，里面有详细的介绍

TWR-K70F120M + TWR-PROTO-ND without TWR-ELEV possible? I have a TWR-K70F120M, can I use the prototype board (TWR-PROTO-ND) without the elevators (TWR-ELEV)? I was wanting to see if I could add some simple passive components by connecting one side of the prototype board to one side of the K70 board. Re: TWR-K70F120M + TWR-PROTO-ND without TWR-ELEV possible? Hi, This is the schematics of TWR-PROTO: https://www.nxp.com.cn/downloads/en/schematics/SCH-26187.pdf The TWR-ELEV board can connect the primary side signals of TWR-K70F120M to the TWR-PROTO board. If you do not want to use TWR-ELEV, pls refer to  the schematics of TWR-K70F120M and check if you can connect the signals of TWR-K70F120M to the TWR-PROTO board, in other words, if the signals on TWR-K70F120M board you want to connect to are connected to a connector on the TWR-K70F120M board so that you can use flying cable to connect them. so it is case by case. Hope it can help you BR XiangJun Rong  

RPA tool - how to generate "relaxed" LPDDR4 timing? What's the best way to use the RPA spreadsheet tool to create "relaxed" LPDDR4 timing? By that I mean timings with more than the usual margin, to allow for more (component / temp / etc) variabilities? I can think of two possible ways, but I don't know if one is better than the other, or even valid. 1. Specify a lower "clock cycle frequency" eg 1400 MHz instead of the default 1500 MHz. Then put a corresponding value in the "DDR Stress Test File" tab DRAM_PLL_FDIV_CTL0 register cell for that frequency. So the bus runs at 1400 MHz using 1400 MHz timing values. 2. Leave the clock cycle frequency at 1500 MHz, and generate the register values for that. But edit the "DDR Stress Test File" tab DRAM_PLL_FDIV_CTL0 register cell for a lower freq, eg 1400 MHz. So the iMX8 runs the bus at 1400 MHz but uses 1500 MHz timing values. Any comments or suggestions? Thanks. Re: RPA tool - how to generate "relaxed" LPDDR4 timing? @frank_vanhooft Here you need use the method 1 to generate timing. If you want to change DDR clock, you should use new frequency DDR configuration and clock setting both at same time. Hope this can do help for you Re: RPA tool - how to generate "relaxed" LPDDR4 timing? iMX8 Mini,  the MIMX8MM6DVTLZAA   Thanks. Re: RPA tool - how to generate "relaxed" LPDDR4 timing? OK, I will help confirm, which product are you using, i.MX8MP or others? Re: RPA tool - how to generate "relaxed" LPDDR4 timing? In my question above, is either option, 1 or 2, better than the other? Or is there another, better, third option? Thanks. Re: RPA tool - how to generate "relaxed" LPDDR4 timing? You can refer to this https://community.nxp.com/t5/i-MX-Processors-Knowledge-Base/iMX-8M-Mini-Register-Programming-Aid-DRAM-PLL-setting/ta-p/1112094

i.MX Security Reference Design Clarification Questions Hello, We implemented the security reference design described in section 10.9 of i.MX Linux User's Guide. Our custom board is based on the imx8mn_evk machine, and the image complies and boots successfully. However, we have questions based on the security-related messages we see during boot (see attached screenshot): Does "No HAB Events Found!" message mean a successful image authentication? Does the meta-secure-boot layer automatically program the SRK tabe hash fuse, or do we need to do this ourselves? We think we have to program the SRK hash fuse ourselves, but if that is the case, how come we got a successful authentication (assuming "No HAB Events Found!" means successful authentication)? We tried to read the SRK hash fuse (fuse 0x580 [256 bits]) to verify, but we always read zeros using uboot `fuse read` command. Is there a way to read this fuse? Thank you, i.MX 8M | i.MX 8M Mini | i.MX 8M Nano Security Re: i.MX Security Reference Design Clarification Questions After some troubleshooting, the answers are summarized below: Yes No Because HAB 4.1.2 and higher only perform a hash check if SRK keys are not zeros. In this case, the SRK fuse was not programmed, defaulting to zero and, therefore, bypassing the hash check. This is only supported by the table posted below from @Harvey021. I can't find it in AN4581, but it matches what we are experiencing. @Harvey021, could you post the source of that table? A reset is required to read the fuse; otherwise, it reads zero. The combination of 3 and 4 made us doubt if we had a proper image before closing the device. We really wanted to see an intentional authentication failure. The only way to do this is to program the fuse and then generate an image with a different SRK table. Then, you will get the authentication failure messages as shown below. Re: i.MX Security Reference Design Clarification Questions AN4581: i.MX Secure Boot on HABv4 Supported Devices (nxp.com) Or search "AN4581" from nxp.com Have you reset the board before read it?  Please share more details about how you program SRK fuse hashs. Regards Harvey Re: i.MX Security Reference Design Clarification Questions @Harvey021, where did you get the table you copied (5.5.1)? This was not included in AN4581.We are familiar with AN4581, but it does not provide answers to our issue. Have you attempted secure boot on imx8mn EVK? Were you able to read back the SRK fuse after programming, or did you get zeros as well?  Re: i.MX Security Reference Design Clarification Questions Please refer to the AN4581. Regards Harvey Re: i.MX Security Reference Design Clarification Questions Please answer, "Based on this clarification, how come we are passing authentication when the fuse is all zero?" Also, we attempted to program the fuse using uboot fuse commands, but we are still reading zeros. Re: i.MX Security Reference Design Clarification Questions Q1, correct.  Q4, zeros means that there are no fuses hash burned. Regards Harvey Re: i.MX Security Reference Design Clarification Questions This response confirms that the meta-secure-boot layer provided in the security reference design dose not program the SRK fuse and we would have to do it ourselves. Based on this clarification how come we are passing authentication when the fuse is all zero? The statement “HAB (some versions and open device) won't compare SRK table against fuses when fuses are 0's.” does not agree with the statement “All HAB functions are executed as for a closed device.” mentioned in section 6.1.2.5 in imx8mn reference manual. Can you clarify? No answers were given to questions 1 and 4. Could you please provide answers.  thank you. Re: i.MX Security Reference Design Clarification Questions Hi,  HAB (some versions and open device) won't compare SRK table against fuses when fuses are 0's. That is correct, we have to burn SRK hash.  Without burning SRK hash, we will not get complete authentication. I think that the reference from Linux User guide mainly focus on the image signing with automation with Yocto build. Regards Harvey

Mass Storage FRDM-MCXN947 With SD Card Hello, I am currently trying to run a Mass Storage Device example on FRDM-MCXN974 with SD card support and FreeRTOS. I managed to get the standard example to run fine. The code contains two tasks APP_task and USB_DeviceTask, I am trying to reduce this code to only one task, which I have designed as follows: int main(void) { /* Initialize board hardware. */ APP_InitBoard(); USB_DeviceApplicationInit(); usb_echo("Available heap size before task creation: %d bytes\r\n", xPortGetFreeHeapSize()); if (g_msc.deviceHandle) { if (xTaskCreate(USB_DeviceTask, /* pointer to the task */ (char const *)"usb device task", /* task name for kernel awareness debugging */ 9000L / sizeof(portSTACK_TYPE), /* task stack size */ g_msc.deviceHandle, /* optional task startup argument */ 4, /* initial priority */ &g_msc.device_task_handle /* optional task handle to create */ ) != pdPASS) { usb_echo("usb device task create failed!\r\n"); return 1; } } vTaskStartScheduler(); while (1) { ; } return 1; } But It always end with fard-fault in USB_DeviceApplicationInit() as in the attached picture. The original code looked like this: int main(void) { /* board initialization... */ /* task... */ if (xTaskCreate(APP_task, /* pointer to the task */ (char const *)"app task", /* task name for kernel awareness debugging */ 5000L / sizeof(portSTACK_TYPE), /* task stack size */ &g_msc, /* optional task startup argument */ 3, /* initial priority */ &g_msc.application_task_handle /* optional task handle to create */ ) != pdPASS) { usb_echo("app task create failed!\r\n"); } vTaskStartScheduler(); return 1; } void USB_DeviceTask(void *handle) { while (1U) { USB_DeviceTaskFn(handle); } } void APP_task(void *handle) { USB_DeviceApplicationInit(); #if USB_DEVICE_CONFIG_USE_TASK if (g_msc.deviceHandle) { if (xTaskCreate(USB_DeviceTask, /* pointer to the task */ (char const *)"usb device task", /* task name for kernel awareness debugging */ 5000L / sizeof(portSTACK_TYPE), /* task stack size */ g_msc.deviceHandle, /* optional task startup argument */ 5, /* initial priority */ &g_msc.device_task_handle /* optional task handle to create */ ) != pdPASS) { usb_echo("usb device task create failed!\r\n"); return; } } while (1) { } } Did I miss anything? Can I somehow reduce the code just to one task? Thank you very much. Development Board MCXN USB Re: Mass Storage FRDM-MCXN947 With SD Card Thank you, so the best way is to use as a baseline bare-metal example for my project Re: Mass Storage FRDM-MCXN947 With SD Card hi,Doly02 I don't think it's possible that the SD_Init () function is still connected to the FreeRTOS task resource, and the program ends up with a hard failure, and SD card initialization is done in the USB_DeviceApplicationInit() function. You can refer to the frdmmcxn947_dev_msc_disk_bm demo program where the USB_DeviceApplicationInit() function is initialized in main. If you use SD cards in Freertos, ensure that the tasks have enough stack space and do not conflict with other tasks, ensure that the initialization and use of the SD card is thread-safe, and you can use the Mutex provided by FreeRTOS to prevent problems caused by multiple tasks accessing the SD card at the same time. If the SD card initialization is done in one task, and other tasks need to wait for the initialization to complete before using the SD card, then Semaphore or other synchronization mechanism should be used to coordinate the tasks. BR Xu Zhang Re: Mass Storage FRDM-MCXN947 With SD Card Hi XuZhang, thank you for your reply and great support from NXP. I am developing device on FreeRTOS that has two task and each of them uses SD card. When I move the initialization to the main (to not initialize SD card twice), there is probably still issue that SD_Init() function still has a connection to FreeRTOS task resources, and program ends up in hard-fault, is that possible? Re: Mass Storage FRDM-MCXN947 With SD Card hi，Doly02 Thank you for your interest in NXP Semiconductor products and the opportunity to serve you, I will gladly help you with this. You can try to modify the frdmmcxn947_dev_msc_disk_freertos demo program in the way shown in the picture. Wish it helps you. If you still have question about it,please kindly let me know. BR Zhang Xu Re: Mass Storage FRDM-MCXN947 With SD Card

Support for 4G LTE module with i.MX8M series in Windows 10 IoT Hi team May I ask which 4G LTE M.2/mini-PCIe interface modules have been verified on Windows 10 IoT? I would like to verify them on the IMX8MQ EVK and IMX8MP EVK. Thaknks for helps James i.MX 8 Family | i.MX 8QuadMax (8QM) | 8QuadPlus i.MX 8M | i.MX 8M Mini | i.MX 8M Nano Windows 10 IoT Enterprise Re: Support for 4G LTE module with i.MX8M series in Windows 10 IoT Hello, So far, there is nothing on the schedule. Regards Re: Support for 4G LTE module with i.MX8M series in Windows 10 IoT Hi Bio_TICHSL, Thanks for yuor reply. Does NXP have a testing plan for 4G LTE / 5G  modules on Windows 10 IoT? Re: Support for 4G LTE module with i.MX8M series in Windows 10 IoT Hello, All i.MX8 have been validate to work with PCIe, we have not tested the LTE for 4G but check the errata of this WinIoT version, Limitation: PCIe DMA supports 32-bit addressing only. Connected PCIe devices using memory > 4 GB may work incorrectly. Workaround: Allocate memory for PCIe devices below 4G or copy data to lower address space in the device driver. More information: https://www.nxp.com/docs/en/release-note/IMXWNR.pdf Regards

レジスタ範囲は編集可能かどうか MC9S12DT256CPVE 0x0-0x3ffの範囲はレジスタですが、すべてのFFに書き込むことができますか?これは、あるチップを別のチップにコピーするときに問題になりますか?

S32K144W problems with custom SPI driver Hi NXP community! I'm developing a custom SPI driver based on the SPI example from the AN5423 application note (https://www.nxp.com/docs/en/application-note/AN5413.pdf) The problem I'm facing is that after initializing, the SPI is only able to send around 23 bytes of data, no matter what I set as the frame size in the Transmit Command Register (TCR). After that, the clock remains in high state even though I set its polarity as SCK low. While debugging, I found that it gets stuck waiting for the TDF flag of the status register to be 0. Also, the TX fifo seams to be full, but I don't know why it is not sending this data. Here is my code: static void* SPI_s_vSelectModule(uint8 u8SpiModule){ void *pAddress = (void*)NULL; if(u8SpiModule == (uint8)SPI_enSPI0){ pAddress = (void*)LPSPI0_BASE_ADDR_cfg; } else if(u8SpiModule == (uint8)SPI_enSPI2){ pAddress = (void*)LPSPI2_BASE_ADDR_cfg; } else{ /* Nothing to do */ } return pAddress; } void SPI_s_vInitPorts(void){ /* Enable clocks */ PCC->PCCn[PCC_PORTB_INDEX]|=PCC_PCCn_CGC_MASK; /* Enable clock for PORTB */ PCC->PCCn[PCC_PORTC_INDEX]|=PCC_PCCn_CGC_MASK; /* Enable clock for PORTC */ PCC->PCCn[PCC_PORTD_INDEX]|=PCC_PCCn_CGC_MASK; /* Enable clock for PORTD */ /* Config. SPI0 */ PORTD->PCR[15]|=PORT_PCR_MUX(4); /* Port D15: MUX = ALT4, LPSPI0_SCK reloj */ PORTD->PCR[16]|=PORT_PCR_MUX(4); /* Port D16: MUX = ALT4, LPSPI0_SIN/MISO */ PORTB->PCR[4]|=PORT_PCR_MUX(3); /* Port B4: MUX = ALT3, LPSPI0_SOUT/MOSI */ PORTB->PCR[5]|=PORT_PCR_MUX(4); /* Port B5: MUX = ALT4, LPSPI0_PCS0 */ /* Config. SPI2 */ PORTC->PCR[15]|=PORT_PCR_MUX(3); /* Port C15: MUX = ALT3, LPSPI2_SCK reloj */ PORTC->PCR[0]|=PORT_PCR_MUX(3); /* Port C0: MUX = ALT3, LPSPI2_SIN/MISO */ PORTC->PCR[1]|=PORT_PCR_MUX(3); /* Port C1: MUX = ALT3, LPSPI2_SOUT/MOSI */ PORTC->PCR[14]|=PORT_PCR_MUX(3); /* Port C14: MUX = ALT3, LPSPI2_PCS0 */ } void SPI_vInitMaster(void){ LPSPI_Type *pstSPI; for(uint8 u8x = 0; u8x < SPI_enTotalSPIs; u8x++){ if(u8x == (uint8)SPI_enSPI0){ PCC->PCCn[PCC_LPSPI0_INDEX] = 0; /* Disable clocks to modify PCS ( default) */ PCC->PCCn[PCC_LPSPI0_INDEX] = 0xC6000000; /* Enable PCS=SPLL_DIV2 (40 MHz func'l clock) */ pstSPI = (LPSPI_Type*)SPI_s_vSelectModule(u8x); } else if(u8x == (uint8)SPI_enSPI2){ PCC->PCCn[PCC_LPSPI2_INDEX] = 0; /* Disable clocks to modify PCS ( default) */ PCC->PCCn[PCC_LPSPI2_INDEX] = 0xC6000000; /* Enable PCS=SPLL_DIV2 (40 MHz func'l clock) */ pstSPI = (LPSPI_Type*)SPI_s_vSelectModule(u8x); } else{ /* Nothing to do */ } pstSPI->CR = 0x00000000; /* Disable module for configuration */ pstSPI->IER = 0x00000000; /* Interrupts not used */ pstSPI->DER = 0x00000000; /* DMA not used */ pstSPI->CFGR0 = 0x00000000; /* Defaults: */ /* RDM0=0: rec'd data to FIFO as normal */ /* CIRFIFO=0; Circular FIFO is disabled */ /* HRSEL, HRPOL, HREN=0: Host request disabled */ pstSPI->CFGR1 = 0x00000001; /* Configurations: master mode*/ /* PCSCFG=0: PCS[3:2] are enabled */ /* OUTCFG=0: Output data retains last value when CS negated */ /* PINCFG=0: SIN is input, SOUT is output */ /* MATCFG=0: Match disabled */ /* PCSPOL=0: PCS is active low */ /* NOSTALL=0: Stall if Tx FIFO empty or Rx FIFO full */ /* AUTOPCS=0: does not apply for master mode */ /* SAMPLE=0: input data sampled on SCK edge */ /* MASTER=1: Master mode */ pstSPI->TCR = 0x5000001F; /* Transmit cmd: PCS0, 32bits, prescale func'l clk by 4. */ //pstSPI->TCR = 0x50000007; /* Transmit cmd: PCS0, 32bits, prescale func'l clk by 4. */ /* CPOL=0: SCK inactive state is low */ /* CPHA=1: Change data on SCK lead'g, capture on trail'g edge*/ /* PRESCALE=2: Functional clock divided by 2**2 = 4 */ /* PCS=0: Transfer using PCS0 */ /* LSBF=0: Data is transferred MSB first */ /*pstSPI->TCR = 0x5080001F*/ /* LSBF=1: Data is transferred LSB first */ /* BYSW=0: Byte swap disabled */ /* CONT, CONTC=0: Continuous transfer disabled */ /* RXMSK=0: Normal transfer: rx data stored in rx FIFO */ /* TXMSK=0: Normal transfer: data loaded from tx FIFO */ /* WIDTH=0: Single bit transfer */ /* FRAMESZ=15: # bits in frame = 15+1=16 */ pstSPI->CCR = 0x04090808; /* Clk dividers based on prescaled func'l clk of 100 nsec */ /* SCKPCS=4: SCK to PCS delay = 4+1 = 5 (500 nsec) */ /* PCSSCK=4: PCS to SCK delay = 9+1 = 10 (1 usec) */ /* DBT=8: Delay between Transfers = 8+2 = 10 (1 usec) */ /* SCKDIV=8: SCK divider =8+2 = 10 (1 usec: 1 MHz baud rate) */ pstSPI->FCR = 0x00000003; /* RXWATER=0: Rx flags set when Rx FIFO >0 */ /* TXWATER=3: Tx flags set when Tx FIFO <= 3 */ pstSPI->CR = 0x00000009; /* Enable module for operation */ /* DBGEN=1: module enabled in debug mode */ /* DOZEN=0: module enabled in Doze mode */ /* RST=0: Master logic not reset */ /* MEN=1: Module is enabled */ } SPI_s_vInitPorts(); } uint16 SPI_u8Transmit(uint8 u8SpiModule, uint8 *data, uint16 size) { uint16 u16Return = (uint16)NOT_OK; LPSPI_Type *pstSPI; uint32 buffer=0; if(u8SpiModule < (uint8)SPI_enTotalSPIs){ pstSPI = (LPSPI_Type*)SPI_s_vSelectModule(u8SpiModule); if(pstSPI != NULL){ // Clean Tx buffer pstSPI->CR |= 1 << LPSPI_CR_RTF_SHIFT; // Configure the FRAMESZ based on the input size pstSPI->TCR = 0x50000000 | (size*8 - 1); //vSpiDelayMs(5); // Send all 32-bit frames that we can handle for(int i=0; i<(size / 4); i++) { buffer = data[4*i + 0] << 24; buffer |= data[4*i + 1] << 16; buffer |= data[4*i + 2] << 8; buffer |= data[4*i + 3]; /* Espera al que este libre */ while((pstSPI->SR & LPSPI_SR_TDF_MASK)>>LPSPI_SR_TDF_SHIFT == 0); /* Transmit data */ pstSPI->TDR = buffer; /* Se limpia la bandera TDF */ pstSPI->SR |= LPSPI_SR_TDF_MASK; } // send remaining bytes if(size%4 > 0) { buffer = 0; // Send the remaining data for(int i=(size%4); i>0; i--) { buffer |= data[size - i] << (8*(i-1)); } while((pstSPI->SR & LPSPI_SR_TDF_MASK)>>LPSPI_SR_TDF_SHIFT == 0); pstSPI->TDR = buffer; /* Se limpia la bandera TDF */ pstSPI->SR |= LPSPI_SR_TCF_MASK; } // Clean complete flag pstSPI->SR |= 1 << LPSPI_SR_TCF_SHIFT; u16Return = (uint16)OK; } else{ /* Nothing to do */ } } else{ /* Nothing to do */ } return u16Return; } uint8 u8Data[] = {0x01U, 0x02U, 0x03U, 0x04U, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F, 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F}; int main(void) { WDOG_Disable(); SOSC_init_8MHz(); /* Initialize system oscillator for 8 MHz xtal */ SPLL_init_160MHz(); /* Initialize SPLL to 160 MHz with 8 MHz SOSC */ NormalRUNmode_80MHz(); /* Init clocks: 80 MHz SPLL & core, 40 MHz bus, 20 MHz flash */ SPI_vInitMaster(); SPI_u8Transmit((uint8)SPI_enSPI0, u8Data, sizeof(u8Data)); SPI_u8Transmit((uint8)SPI_enSPI0, u8Data, sizeof(u8Data)); while(1) { vDelayMs(500); } } And here are some readings from a logic analyzer: I've been struggling with this for weeks. I'd really appreciate if you can tell me if I'm missing something Re: S32K144W problems with custom SPI driver That seems to solve the issue. Thanks! Re: S32K144W problems with custom SPI driver Hi @marco_medrano, Try masking the RX data (TCR[RXMSK] = 1). I don't see any code that would read RDR. Thank you, BR, Daniel

i.MX6ULL eMMC Flash and Boot We have made a custom board with i.MX6ULL EVK and specifically the CM module of the EVK as reference. On our board we have a QSPI Memory (same MPN as the EVK CM) and a eMMC (THGBMUG6C1LBAIL).  When we try to flash the Linux Image (LF_v6.6.36-2.1.0_images_IMX6UL7D.zip) using UUU, it looks like the U-Boot is being flashed, but not the Linux Image, and then it goes into a continuous loop.  On the same board we are able to flash to QSPI using mfgtools and a baremetal sdk example "hello world" and the same is running fine on the QSPI.  Any pointers on what should be done to resolve this will be great.  i.MX6 All i.MX6UL Linux Windows Yocto Project Re: i.MX6ULL eMMC Flash and Boot To anyone following this, or facing similar issues, we found out that our issue was that UBoot was crashing and hence the USB error and connected issues.  The Uboot crashing in turn was because the EVK DTS was configured for Ethernet PHY addresses in a particular way and we had them wired in a different way on our custom board. Once we resolved the Ethernet PHY address issue and changed as per the EVK, the UBoot crash stopped and we were able to flash the eMMC. Re: i.MX6ULL eMMC Flash and Boot Hi @ET_Dev! Yes, you have to adapt some things like ddr timing, etc. Maybe you don't have to adapt all the BSP but is necessary to adapt according to your hardware. Best Regards! Chavira Re: i.MX6ULL eMMC Flash and Boot Hello Chavira Thanks for looking at this. I understand that the image is for NXP boards, I read the same on other posts as well.  However, in this case we have followed and replicated the EVK schematic as it is, with the only exception of populating a eMMC which is not populated on the EVK CM. Do you think even in this case the NXP image will not work? Re: i.MX6ULL eMMC Flash and Boot Hi @ET_Dev! Thank you for contacting NXP Support! The LF_v6.6.36-2.1.0_images_IMX6UL7D.zip is only for our boards. If you want to boot your board you have to customize our BSP according to your board. You can refer to our PORTING GUIDE to port our BSP to your board. Best Regards! Chavira

TJA1043 Power On Hi. We use a TJA1043. I have a question about INH pin. Vbat is turned on, and then Vcc and Vio are turned on with a delay(about 20msec). At this time, INH pin is output at the same time as Vbat. Is this correct behavior? I thought that INH pin would be output after Vcc and Vio were established, but is that correct? (Vbat = 24V, Vcc = 5V, Vio = 3.3V, STB pin = pull down, EN pin = pull up) Best regards. Re: TJA1043 Power On Hi. Thank you for answer. I'll check AH1014 data. Best regards. Re: TJA1043 Power On Hi, Vbat power on is described in AH1014 BR, Petr

S9KEAZ series into MCUXPRESSO Dear All. Is it a way to create a project into MCUXpresso for the S9KEAZN32ACLC MCU? I mean, using the standard way that is to create a SDK and build overt it? OR, maybe, by using the "generic M0+" entry? Hints welcome. Best regards. Jorgecon Re: S9KEAZ series into MCUXPRESSO Thanks, Zhang. It is clear. Re: S9KEAZ series into MCUXPRESSO Hello Jorgecon, MCUXPRESSO doesn't support S9KEAZ series. This series is automotive MCU which is supported by S32DS https://www.nxp.com/design/design-center/software/automotive-software-and-tools/s32-design-studio-ide/s32-design-studio-for-arm:S32DS-ARM the related BSP and drivers are under  "Embedded Software" of this page https://www.nxp.com/products/processors-and-microcontrollers/arm-microcontrollers/automotive-mcus/ultra-reliable-kea-automotive-microcontrollers-mcus-based-on-arm-cortex-m0-plus-core:KEA Hope this helps, Jun Zhang

Debugging an i.MX8MPlus Cortex-M7 core on the EVK. Hello all, I am working on setting up my development and debugging environment for the Cortex-M7 core of the i.MX 8M Plus.  I have successfully generated an SDK using the online NXP SDK builder tool, and I am able to open and build the FreeRTOS hello world example using the NXP MCUXpresso VSCode plugin.  However, I have not been able to flash or debug the i.MX 8M Plus on my EVK. I was able to use J-Link Commander with a rev 1.2 J-Link Ultra to confirm SWD communication was working, but I was unable to flash or debug, as Segger does not support debugging Cortex-M7 cores with this hardware revision.  I have since ordered an NXP MCU-Link Pro debugger, but I am having issues getting debugging going with that as well. Should the NXP MCU-Link Pro be able to debug the Cortex-M7 core of an i.MX 8M Plus? If not, what debugging probes are known to support JTAG or SWD debugging the Cortex-m7 core of an i.MX 8M Plus? Re: Debugging an i.MX8MPlus Cortex-M7 core on the EVK. I ordered a J-Trace Cortex and was able to debug successfully. I also had to follow section 4 of the AN14120 .pdf you linked above to debug without reset. Re: Debugging an i.MX8MPlus Cortex-M7 core on the EVK. Hi, Thank you for your interest in NXP Semiconductor products, I have a reference of a j-link plus working, do you have one handy to test it? Could you please follow the guide attached and pass the record with pro and possibly with plus? Notice that also in this post is stated that it's worked with plus. Regards

Can I get the S32K3XX Driver? Hello, @Robin_Shen  I am currently developing firmware for the S32K314 series without using the RTD. While searching for clock drivers, I came across a response you posted and checked the project. It seems that there is a driver folder in the project, which leads me to believe that there might be drivers available for the non-RTD version. Is there any way I can get access to the drivers for each module? Re: Can I get the S32K3XX Driver? thank you for answer! Re: Can I get the S32K3XX Driver? Hi The Baremetal Example Codes used to be available for download from docstore.nxp.com. But this was before the release of S32K3 RTD and is no longer available for download and is not recommended.  Best Regards, Robin ------------------------------------------------------------------------------- Note: - If this post answers your question, please click the "Mark Correct" button. Thank you! - We are following threads for 7 weeks after the last post, later replies are ignored Please open a new thread and refer to the closed one, if you have a related question at a later point in time. -------------------------------------------------------------------------------

Updating DDR-PHY Firmware NOR Flash Address Location in Custom LX2160a Board Hi, I'm currently working on a custom board utilizing the LX2160a processor with an XSPI flash to store firmware and boot from it. Looking into the NOR flash address location for the DDR-PHY firmware within the LSDK, I've noticed that it's set to 0x00800000. However, for our custom board's requirements, we need it to be at 0x00500000 instead. Attaching the LSDK NOR-Flash Map. I've attempted to locate this address within the Arm Trusted Firmware (ATF) repository, as BL2 handles the loading of this firmware, but I've been unable to find it. Does anyone have information on how to update the DDR-PHY firmware NOR flash address location? I assume it must be somewhere within the ATF repository since BL2 loads this firmware. Any guidance or pointers would be greatly appreciated. Thank you, Re: Updating DDR-PHY Firmware NOR Flash Address Location in Custom LX2160a Board Our custom board has 256 MB of flash so I was using this address. I used 0x500000 address location and it works fine. Thank you. Not sure if atf doesn't support flash after 64MB. Re: Updating DDR-PHY Firmware NOR Flash Address Location in Custom LX2160a Board It seems that the offset 0x8800000 exceeds the size of XSPI NOR flash. Re: Updating DDR-PHY Firmware NOR Flash Address Location in Custom LX2160a Board Thank you for the response.  I did try that before and I tried to do again when you suggested now.  That MACRO is not having any impact on the location of DDR-PHY.  I generated a pbl with the suggested change and then erased the DDR phy from default location 0x800000 and flashed the image at a custom location 0x8800000. I see the below error. It is unable to find the PHY firmware to train. INFO: pll_ctrl2 = 0x19 INFO: SOC_SI_REV = 2 INFO: dll_lck_param = 0x212 INFO: dll_gain_ctl = 0x61 INFO: prog_acx4_anib_dis 0x0 INFO: Initialize PHY 1 config INFO: pll_ctrl2 = 0x19 INFO: SOC_SI_REV = 2 INFO: dll_lck_param = 0x212 INFO: dll_gain_ctl = 0x61 INFO: prog_acx4_anib_dis 0x0 INFO: Load 1D firmware WARNING: Firmware Image Package header check failed. WARNING: Failed to obtain reference to image id=36 (-2) ERROR: Failed to load 36 firmware. ERROR: Loading firmware failed (error code -2) ERROR: Calculating DDR PHY registers failed. INFO: Time before programming controller 401 ms INFO: Program controller registers INFO: Disable address decoding INFO: PHY handshake completed, timer remains 40 INFO: total size 16 GB INFO: Need to wait up to 2840 ms ERROR: Found training error(s): 0x100 ERROR: Error: Waiting for D_INIT timeout. ERROR: Writing DDR register(s) failed ERROR: Programing DDRC error ERROR: DDR init failed. ERROR: Asserting as the DDR is not initialized yet.ASSERT: plat/nxp/common/setup/ls_bl2_el3_setup.c:285 BACKTRACE: START: assert 0: EL3: 0x18017240 1: EL3: 0x1801a668 2: EL3: 0x18015a84 3: EL3: 0x1800da6c 4: EL3: 0x1800d108 BACKTRACE: END: assert Re: Updating DDR-PHY Firmware NOR Flash Address Location in Custom LX2160a Board In atf source code, please modify the following in plat/nxp/common/fip_handler/ddr_fip/ddr_io_storage.h. #define PLAT_DDR_FIP_OFFSET 0x800000

How to display dsi to dual lvds using sn65dsi84? Hi, I would like to use sn65dsi84 to display mipi-dsi as dual-link lvds. However, only imx8m reference can be found. My processor is imx8qxp, using custom bsp in linux kernel 5.15.71. I found some imx8m references, but I don't know how to migrate to imx8qxp. For example, in the sample dts below, I don't know what the replacement for &mipi_dsi_bridge is. ------------------------------- &mipi_dsi_bridge { status = "okay";   port@2 {     mipi_dsi_bridge_out: endpoint {       remote-endpoint = <&sn65dsi84_in>;     };   }; }; ------------------------------- Can I find imx8qxp reference using sn65dsi84? Thanks in advance. Re: How to display dsi to dual lvds using sn65dsi84? Hi @hansung_jung  Please find arch/arm64/boot/dts/freescale/imx8x-mek.dtsi and refer adv7535 node to port your sn65dsi84 node. &mipi0_dsi_host { status = "okay"; ports { port@1 { reg = <1>; mipi0_adv_out: endpoint { remote-endpoint = <&adv7535_0_in>; }; }; }; };

about S32K3XX RTOS example i'm tried to executed the RTPS_example_S32K312_SC1/RTOS_example_S32K312_SC1 I DID EB tresos.exe and install new software Added a file whose file name ends with updatestie. generate the new project and then build project  but i meet the error be called the file Os.h not in this proejct. and in peripherals RTOS_S32K3XX is not found in the toolcahin/IDE project. the project will not compile! what can i do to solve the error? Re: about S32K3XX RTOS example Hi i figure out i missed to download s32m27X RTM in freeRTOS 10.6.0. Thank  you. Re: about S32K3XX RTOS example Hi  Seems that you are testing the example of S32K3xx_NXP_RTOS_version_0.4.1 Maturity level is CD. This is CD NXP RTOS 0.4.1 release for S32K3xx platform to support AUTOSAR OS version 4.4 validated on real hardware. Did you follow the method introduced in chapter 1.2.1 Installation Design Studio of S32K3xx_NXP_RTOS_4_4_153_CODEDROP_0_4_1_D2312_Readme.pdf? Best Regards, Robin ------------------------------------------------------------------------------- Note: - If this post answers your question, please click the "Mark Correct" button. Thank you! - We are following threads for 7 weeks after the last post, later replies are ignored Please open a new thread and refer to the closed one, if you have a related question at a later point in time. -------------------------------------------------------------------------------

如何找到已安装 SDK 的确切位置？ 我正在阅读“EVK-MIMXRT1060 的 MCUXpresso SDK 入门”，这篇文章介绍了包文件夹和每个示例的结构。 我尝试从已安装 SDK 窗口打开已安装 SDK 的本地位置，但只有 .zip文件。我尝试使用 Welcome | MCUXpresso SDK Builder (nxp.com) 从互联网下载 SDK，我解压了 .zip文件，还有一些示例文件夹。在哪里可以找到安装在 MCUXpresso IDE 中与 .zip 相同的示例文件夹文件？ 此外，我还检查了 IDE 中的 hello_world 文件夹结构和 hello_world 项目结构。这太不同了。在IDE中，有很多文件夹，例如“board”，“component”，“device”......您可以在所附图片中看到。例如，IDE 中有文件“semihost_hardfault.c”，但 .zip 的 hello_world 文件夹中没有此文件文件。如何了解IDE中项目的结构？现在我无法从文件夹（.zip将文件复制到 IDE。 抱歉我的英语不太好。谢谢。