USB Audio Device with multiple streaming interfaces I'm hitting exactly the same issue as this post Usb Audio Device - Multiple ISO interfaces IN/OUT - NXP Community and it is kind of astonishing that apparently this has not yet been fixed since 2018. The problem with the current USB software stack is that the `usb_device_audio_struct_t` is assuming that we are always dealing with one single streaming interface which number is stored into `streamInterfaceNumber`. This is definitely not the case as pointed out in that issue. So is there any new example or guide on how to correctly implement the case in which we have multiple streaming interfaces? i.MXRT 600 Re: USB Audio Device with multiple streaming interfaces Yeah, I modified the USB framework code myself but it would be better to address this limitation in the examples. Re: USB Audio Device with multiple streaming interfaces Hi @carlocaione, I'm afraid we don't have an example code or guide for the process you are trying to achieve with multiple streaming interfaces. Just like the post you referenced suggested; you would have to make this change manually. Sorry for the inconvenience this may cause. BR, Edwin.

S32K3XX periodic interrupt I' m trying to implement a periodic interrupt by means of the PIT timer. I have started from the S32K344_pwm_led_ebt example. From what I understand in this example, the Gpt_PitNotificationis hanging from PIT0 device. The problem is that the notification is being generated at a 250mHz, no matter the frequency that I configure in the GptChannelTickFrequency (S32 configuration tool) or the Gpt_start_timer Simulink block. How do you change the timer periode? Thanks in advance. Re: S32K3XX periodic interrupt Hello @Alfredo_Rubio  The GptChannelTickFrequency parameter corresponds to the frequency of the clock being used for the specific timer channel, selected by the GptChannelClkSrcRef configuration parameter. Hence, for changing the value of the GptChannelTickFrequency, a new source clock must be selected for the specific Gpt channel, or the frequency value for the already selected clock must be edited inside the Clocks Tool. The Gpt Simulink block allows the specification of a time-out period (in number of ticks), for the selected Channel, after which a notification should occur. Hence, changing the Value parameter of the Simulink block should also vary the period of execution for the notification function associated to that channel. Could you please let us know what Gpt channel are you using inside your model? Is it the GptChannelConfiguration_0 already enabled inside the configuration project associated to that model or have you configured a different one? Also, what is the action being executed inside that subsystem, i.e how do you measure the 250 mHz for the notification period? For reference, please check the Gpt examples that our toolbox provides, found inside the /S32K3_Examples/gpt folder, for seeing more details on how these functions are used inside a Simulink model. Thank you, Irina

IMX RT1170B First Boot Code Execution We have a custom IMXRT1170 board based on the EVK that works great when I use LPCLink / MCUXpresso to program the board for the first time. After programming them once with the LPCLink we can use either the LPCLink or JLINK programmers without issue. However, code will not execute using the JLINK programmer until they are programmed with the LPCLink programmer once. The registers look like this if after are programmed with the JLINK: PC = 300024BC, CycleCnt = 0B04C872 R0 = 40CAC0B0, R1 = 0A000000, R2 = 80000000, R3 = 0000F000 R4 = E000ED00, R5 = 0022946D, R6 = 001640CD, R7 = 00207DC8 R8 = 2024AE80, R9 = 2024AE84, R10= 00211C0C, R11= 000000F0 R12= 00000000 SP(R13)= 82F80000, MSP= 82F80000, PSP= 00000000, R14(LR) = 002015F3 XPSR = 81000000: APSR = Nzcvq, EPSR = 01000000, IPSR = 000 (NoException) CFBP = 00000001, CONTROL = 00, FAULTMASK = 00, BASEPRI = 00, PRIMASK = 01 FPS0 = 00000000, FPS1 = 00000000, FPS2 = 00000000, FPS3 = 00000000 FPS4 = 00000000, FPS5 = 00000000, FPS6 = 00000000, FPS7 = 00000000 FPS8 = 00000000, FPS9 = 00000000, FPS10= 00000000, FPS11= 00000000 FPS12= 00000000, FPS13= 00000000, FPS14= 00000000, FPS15= FFFFFFFF FPS16= 00000000, FPS17= 00000000, FPS18= 00000000, FPS19= 00000000 FPS20= 00000000, FPS21= 00000000, FPS22= 00000000, FPS23= 00000000 FPS24= 00000000, FPS25= 00000000, FPS26= 00000000, FPS27= 00000000 FPS28= 00000000, FPS29= 00000000, FPS30= 00000000, FPS31= FFFFFFFF FPSCR= 00000000 These look OK to me but code doesn't execute. Upon Reset: PC = 00223104, CycleCnt = 9CDD4732 R0 = 40CAC0B0, R1 = 0A000000, R2 = 80000000, R3 = 0000F000 R4 = E000ED00, R5 = 0022946D, R6 = 001640CD, R7 = 00207DC8 R8 = 2024AE80, R9 = 2024AE84, R10= 00211C0C, R11= 000000F0 R12= 00000000 SP(R13)= 20241D98, MSP= 20241D98, PSP= 00000000, R14(LR) = 002015F3 XPSR = 81000000: APSR = Nzcvq, EPSR = 01000000, IPSR = 000 (NoException) CFBP = 00000001, CONTROL = 00, FAULTMASK = 00, BASEPRI = 00, PRIMASK = 01 FPS0 = 00000000, FPS1 = 00000000, FPS2 = 00000000, FPS3 = 00000000 FPS4 = 00000000, FPS5 = 00000000, FPS6 = 00000000, FPS7 = 00000000 FPS8 = 00000000, FPS9 = 00000000, FPS10= 00000000, FPS11= 00000000 FPS12= 00000000, FPS13= 00000000, FPS14= 00000000, FPS15= FFFFFFFF FPS16= 00000000, FPS17= 00000000, FPS18= 00000000, FPS19= 00000000 FPS20= 00000000, FPS21= 00000000, FPS22= 00000000, FPS23= 00000000 FPS24= 00000000, FPS25= 00000000, FPS26= 00000000, FPS27= 00000000 FPS28= 00000000, FPS29= 00000000, FPS30= 00000000, FPS31= FFFFFFFF FPSCR= 00000000 I see from reading the example .scp files from NXP that PC = 00223104 indicates the processor is still in some sort of debug mode. Trying to follow the example from the connect m7 wake m4 and reset scp scripts, I am running the following commands in JLINK for the first execution: device MIMXRT1176XXXA_M4 si SWD speed 4000 connect Halt Write4 0x2021FF00 0xE7FEE7FE Write4 0x2021FF04 0x2021FF01 Write4 0x40C0C000 0xFF00 Write4 0x40C0C004 0x2021 Write4 0x40CC0080 0x201 Reset Go Exit Device MIMXRT1176XXXA_M7 si SWD speed 4000 Connect LoadFile hello.elf WReg “R13 (SP)”, 0x82F80000 WReg “R15 (PC)”, 0x300024BD WReg “XPSR”, 0x01000000 Write4 0x40C0C068 0x4200 Write4 0xE000EDFC 0x010007F1 Halt Reset Go But I still get the same result. The register settings look correct after writing, but code doesn't execute, and upon reset I still get the PC = 00223104 issue. Our production stations use JLINK programmers and so we need to be able to start the boards up with them. What other registers or addresses do I need to be writing to get the rev B processor out of debug mode permenantly? Thank you. Re: IMX RT1170B First Boot Code Execution I figured it out, and thought I would share in case someone else needs the information. Turns out the IMX RT family needs a separate flashloader program that lives on-chip to correctly program external flash. MCUXpresso uses their internal flashloader which is why we needed to use their tool to boot first. But, it turns out an NXP engineer also wrote a flashloader for the IMX RT family to work with JLink: https://github.com/JayHeng/RT-UFL/blob/master/README-en.md Instructions on how to use it are here (note that this is for the RT600 but the basic steps are identical): https://community.nxp.com/t5/i-MX-RT-Knowledge-Base/RT600-MCUXpresso-JLINK-debug-QSPI-flash/ta-p/1345484 Only unfortunate thing is this flashloader hasn't been updated for a while, and I had to revert to JLINK version 7.60d in order to get it to work. Re: IMX RT1170B First Boot Code Execution Hi Pavel, I do not believe this is a confused core issue, and our project only uses the M7 core. I am setting the M4 spin codes only to prevent its interrupts from interfering with the M7 per the comments in the reset and connect scripts from NXP. There's actually a pretty good comment from NXP in the header of the reset.scp script for the IMX RT 1170 explaining what's going on here: 1 REM ====================================== 2 REM Copyright 2020-2023 NXP 3 REM All rights reserved. 4 REM SPDX-License-Identifier: BSD-3-Clause 5 REM ====================================== 100 REM IMXRT1170 Reset script 110 REM When RT1170 Rev B is reset via SYSRESET_REQ under debugger control, bootROM will 120 REM not boot an existent flash application, instead it will enter a debug loop at a 130 REM fixed PC address (0x00223104). The debugger then needs to initialise the execution 140 REM context in order to jump to the user application. 150 REM RT1170 Rev A does not present this functionality, so it is allowed to continue 160 REM the booting process without any other intervention post reset. Per this comment, the "The debugger then needs to initialise the execution context in order to jump to the user application." is the bit I am having trouble with. Like I said, I copied the register writes present in this same reset.scp script into my own custom JLINK script, and confirmed the writes are successful, but this is still evidently not enough to "initialize the execution context in order to jump to the user application." Perhaps you could contact the author of this IMXRT 1170 reset.scp script for more detail about what needs to be done? Re: IMX RT1170B First Boot Code Execution Hello, maybe need to recover control, indicates the processor is still in some sort of debug mode could you try to do the steps on the thread? RT board recovery for debugger connect issues - NXP Community Does this mean you are working on a dual-core project? Trying to follow the example from the connect m7 wake m4 and reset scp scripts, I am running the following commands in JLINK for the first execution: If yes, maybe this thread could help you. How to use JLINK to debug RT1170 dual core - NXP Community Best regards, Pavel Re: IMX RT1170B First Boot Code Execution Hi Pavel, I am not exactly sure if this is what you are asking - I am unsure how the launcher is relevant as we need to use JLink Commander to program with the JLink probe, not MCUXpresso. JLink Commander/JLink is our production tool and so we need to be able to program with that toolset. Our code is also not built in MCUXpresso, so again I don't think the launcher is relevant. In case this is what you are after, here is the output from a successful programming via MCUXpresso / LPCLink (i.e. the first time programming after which all subsequent programming work regardless of the method). Executing flash operation 'Program' (Program file into flash: test_ads1119.elf) - Thu May 02 14:13:52 PDT 2024 Checking MCU info... Scanning for targets... Executing flash action... MCUXpresso IDE RedlinkMulti Driver v11.9 (Dec 11 2023 18:02:10 - crt_emu_cm_redlink.exe build 2) ( 0) Reading remote configuration Wc(03). No cache support. Found chip XML file in C:/Users/breste60576/Documents/MCUXpressoIDE_11.9.0_2144/workspace/evkmimxrt1170_freertos_generic_cm7\MIMXRT1176xxxxx.xml ( 5) Remote configuration complete Reconnected to existing LinkServer process. ============= SCRIPT: RT1170_connect_M7_wake_M4.scp ============= RT1170 Connect M7 and Wake M4 Script DpID = 6BA02477 Error: No power acknowledge on DAP bus Setting M4 spin code Setting M4 clock Resetting M4 core Releasing M4 View cores on the DAP AP DpID = 6BA02477 TAP 0: 6BA02477 Core 0: M7 APID: 84770001 ROM Table: E00FD003* TAP 0: 6BA02477 Core 1: M4 APID: 24770011 ROM Table: E00FF003 ============= END SCRIPT ======================================== Probe Firmware: LPC-LINK2 CMSIS-DAP V5.361 (NXP Semiconductors) Serial Number: IWFWO1ES VID:PID: 1FC9:0090 USB Path: \\?\hid#vid_1fc9&pid_0090&mi_00#9&36d46763&0&0000#{4d1e55b2-f16f-11cf-88cb-001111000030} Using memory from core 0 after searching for a good core ( 30) Emulator Connected ( 40) Debug Halt ( 50) CPU ID debug interface type = CoreSight DP (DAP DP ID 6BA02477) over SWD TAP 0 processor type = Cortex-M7 (CPU ID 00000C27) on DAP AP 0 number of h/w breakpoints = 8 number of flash patches = 0 number of h/w watchpoints = 4 Probe(0): Connected&Reset. DpID: 6BA02477. CpuID: 00000C27. Info: Debug protocol: SWD. RTCK: Disabled. Vector catch: Disabled. Content of CoreSight Debug ROM(s): RBASE E00FD000: CID B105100D PID 000008E88C ROM (type 0x1) ROM 1 E00FE000: CID B105100D PID 04000BB4C8 ROM (type 0x1) ROM 2 E00FF000: CID B105100D PID 04000BB4C7 ROM (type 0x1) ROM 3 E000E000: CID B105E00D PID 04000BB00C Gen SCS (type 0x0) ROM 3 E0001000: CID B105E00D PID 04000BB002 Gen DWT (type 0x0) ROM 3 E0002000: CID B105E00D PID 04000BB00E Gen (type 0x0) ROM 3 E0000000: CID B105E00D PID 04000BB001 Gen ITM (type 0x0) ROM 2 E0041000: CID B105900D PID 04001BB975 CSt ARM ETMv4.0 type 0x13 Trace Source - Core ROM 2 E0042000: CID B105900D PID 04004BB906 CSt type 0x14 Debug Control - Trigger, e.g. ECT ROM 1 E0043000: CID B105900D PID 04001BB908 CSt CSTF type 0x12 Trace Link - Trace funnel/router NXP: MIMXRT1176xxxxx DAP stride is 1024 bytes (256 words) Inspected v.2 External Flash Device on SPI using SFDP JEDEC ID MIMXRT1170_SFDP_QSPI.cfx Image 'iMXRT1170_SFDP_FlexSPI1_A_QSPI Dec 12 2023 17:27:24' Opening flash driver MIMXRT1170_SFDP_QSPI.cfx Sending VECTRESET to run flash driver Flash variant 'iMXRT1170_SFDP_FlexSPI1_A_QSPI Dec 12 2023 17:27:24' detected (16MB = 256*64K at 0x30000000) Closing flash driver MIMXRT1170_SFDP_QSPI.cfx ( 65) Chip Setup Complete Connected: was_reset=true. was_stopped=false ( 70) License Check Complete Loading 'test_ads1119.elf' ELF 0x30000400 len 0x200 Opening flash driver MIMXRT1170_SFDP_QSPI.cfx (already resident) Sending VECTRESET to run flash driver Flash variant 'iMXRT1170_SFDP_FlexSPI1_A_QSPI Dec 12 2023 17:27:24' detected (16MB = 256*64K at 0x30000000) Writing 512 bytes to address 0x30000400 in Flash 1 of 1 ( 0) Writing sectors 0-0 at 0x30000400 with 512 bytes ( 0) at 30000000: 0 bytes - 0/1536 (100) at 30000000: 16384 bytes - 16384/1536 Sectors written: 1, unchanged: 0, total: 1 Erased/Wrote sector 0-0 with 512 bytes in 166msec Closing flash driver MIMXRT1170_SFDP_QSPI.cfx (100) Finished writing Flash successfully. Flash Write Done Loaded 0x200 bytes in 273ms (about 1kB/s) Loading 'test_ads1119.elf' ELF 0x30001000 len 0x30 Opening flash driver MIMXRT1170_SFDP_QSPI.cfx (already resident) Sending VECTRESET to run flash driver Flash variant 'iMXRT1170_SFDP_FlexSPI1_A_QSPI Dec 12 2023 17:27:24' detected (16MB = 256*64K at 0x30000000) Writing 48 bytes to address 0x30001000 in Flash 1 of 1 ( 0) Writing sectors 0-0 at 0x30001000 with 48 bytes ( 0) at 30000000: 0 bytes - 0/4144 (100) at 30000000: 16384 bytes - 16384/4144 Sectors written: 1, unchanged: 0, total: 1 Erased/Wrote sector 0-0 with 48 bytes in 202msec Closing flash driver MIMXRT1170_SFDP_QSPI.cfx (100) Finished writing Flash successfully. Flash Write Done Loaded 0x30 bytes in 310ms (about 0kB/s) Loading 'test_ads1119.elf' ELF 0x30001040 len 0x10 Opening flash driver MIMXRT1170_SFDP_QSPI.cfx (already resident) Sending VECTRESET to run flash driver Flash variant 'iMXRT1170_SFDP_FlexSPI1_A_QSPI Dec 12 2023 17:27:24' detected (16MB = 256*64K at 0x30000000) Writing 16 bytes to address 0x30001040 in Flash 1 of 1 ( 0) Writing sectors 0-0 at 0x30001040 with 16 bytes ( 0) at 30000000: 0 bytes - 0/4176 (100) at 30000000: 16384 bytes - 16384/4176 Sectors written: 1, unchanged: 0, total: 1 Erased/Wrote sector 0-0 with 16 bytes in 199msec Closing flash driver MIMXRT1170_SFDP_QSPI.cfx (100) Finished writing Flash successfully. Flash Write Done Loaded 0x10 bytes in 309ms (about 0kB/s) Loading 'test_ads1119.elf' ELF 0x30002000 len 0x777C Opening flash driver MIMXRT1170_SFDP_QSPI.cfx (already resident) Sending VECTRESET to run flash driver Flash variant 'iMXRT1170_SFDP_FlexSPI1_A_QSPI Dec 12 2023 17:27:24' detected (16MB = 256*64K at 0x30000000) Writing 30588 bytes to address 0x30002000 in Flash 1 of 1 ( 0) Writing sectors 0-0 at 0x30002000 with 30588 bytes ( 0) at 30000000: 0 bytes - 0/38780 ( 42) at 30000000: 16384 bytes - 16384/38780 ( 84) at 30004000: 16384 bytes - 32768/38780 (100) at 30008000: 16384 bytes - 49152/38780 Sectors written: 1, unchanged: 0, total: 1 Erased/Wrote sector 0-0 with 30588 bytes in 363msec Closing flash driver MIMXRT1170_SFDP_QSPI.cfx (100) Finished writing Flash successfully. Flash Write Done Loaded 0x777C bytes in 465ms (about 65kB/s) Reset target (system) ============= SCRIPT: RT1170_reset.scp ============= SYSTEM Reset DpID = 6BA02477 TAP 0: 6BA02477 Core 0: M7 APID: 84770001 ROM Table: E00FD003* TAP 0: 6BA02477 AP 1: APID: 24770011 ROM Table: E00FF003 TAP 0: 6BA02477 AP 2: APID: 54770002 ROM Table: 00000002 APID = 0x84770001 Setting M4 spin code Setting M4 clock Resetting M4 core Releasing M4 View cores on the DAP AP DpID = 6BA02477 TAP 0: 6BA02477 Core 0: M7 APID: 84770001 ROM Table: E00FD003* TAP 0: 6BA02477 Core 1: M4 APID: 24770011 ROM Table: E00FF003 R15 = 0x00223104 Vector table SP/PC is the reset context. PC = 0x300024BD SP = 0x82F80000 XPSR = 0x01000000 VTOR = 0x30002000 Set DEMCR = 0x010007F1 ============= END SCRIPT =========================== Re: IMX RT1170B First Boot Code Execution Hello, could you test the led blinky led and share the LOG file and the popup image is this are showed. In other observations did you erase the Launcher to switch the debugger flavor? Best regards, Pavel

SJA1110 SPI_AP interface Hello,        I see that SJA1110 supports SPI_HOST and SPI_AP access point in the UM11107 software UM for SJA1110.        My hardware is GLDBOX, it's design is S32G274A---SPI---SJA1110        I am not sure if I want to use SPI_AP interface, first I select the Pins SPI_HAP_SSx_N to SPI_HAP_SS0; second if I should connect the external controller's SPI_PER to sja1110's SPI_HAP?        If I use SPI_AP, does SJA1110 can't boot and download image itself? so the external controller must be another SJA1110 and can't be S32J274A, even they have SPI connect? Is my understand right?        Thank you very much!       Re: SJA1110 SPI_AP interface Hello,        Thank you for your reply, yes, I have asked in another topic "SJA1110 SDK for the hardware GLDBOX". Maybe we can discuss there.         Re: SJA1110 SPI_AP interface Hello @yangjinzhuang , you need to say to SDK, how the switchcore can be accessed. Then internal routines (like SWITCH_DRV_Read) take care of that automatically. If you are developing firmware for SJA1110's internal M7, SWITCH_CONTROL_INTERNAL shall be set. If you are developing firmware for SJA1110's internal M7 to access external switchcore (cascaded SJA1110), SWITH_CONTROL_SPI shall be used: I guess it will be about the same if you are developing firmware for S32G to control SJA1110 over SPI. I need to double check it. You have created another thread on that, so I will answer there. Thank you for your patience. Best regards, Pavel Re: SJA1110 SPI_AP interface Hello,         Thank you very much, I am now clearly understand the SPI_AP and boot process. At last, I am not sure about the SWITCH_CONTROL_INTERNAL and SWITH_CONTROL_SPI mode in SDK,  do I need to config it to SWITH_CONTROL_SPI if I want to work on SPI_AP access, I see it set to SWITCH_CONTROL_INTERNAL as default in SDK. Re: SJA1110 SPI_AP interface Hello @yangjinzhuang , Usage of SPI_AP does NOT affect boot from SPI FLASH. ad 1. After reset, the SJA110 reads pin strapping options and boots from SPI FLASH. Then you can access SPI_AP at your will - reading registers, dynamically changing configuration, ... ad 2. You can use 32G274A as an external microcontroller to control SJA1110 through SPI_AP. Yes, the NVM boot will still succeeded. Best regards, Pavel Re: SJA1110 SPI_AP interface Hello @yangjinzhuang , ad 1. External controller can be anyone. I use my laptop & FTDI driver to access my SJA1110 EVM board. ad 2. Once you load image from SPI FLASH, the external microcontroller is not necessary at all. SJA1110 can work fully autonomously. External microcontroller could monitor traffic, diagnostic registers, ...  ad 3. SDL boot is also supported option. Best regards, Pavel Re: SJA1110 SPI_AP interface Hello,        I still has some question about the SPI_AP:        1、Does external microcontroller not must be another SJA1110, S32G274A has SPI access also can be the external microcontroller?       2、On SPI_AP, boot step also load image from SPI flash, run over the init and static config process, etc.  as same as the SPI_HOST mode, then what will the external microcontroller do about the ethernet switch?        3、In my understand that the boot and load image will controlled by external microcontroller, SJA1110 only provides ethernet switch to external microcontroller as hardwares         Re: SJA1110 SPI_AP interface Hello,        Thanks for your reply, from um549820-UM11107 software UM, I got that SPI_HOST and SPI_AP are multiplexed, because SPI_HOST is used to control the processor boot, then if I set SPI_AP and switch is controlled by external microcontroller, so I understand that SPI_AP has an impact on boot step, maybe my understand is not right, so I need your help to confirm.        1、I see my hardware, the dip switch SW12[1] is on and SW12[2] is off in default, it's boot mode is NVM boot and boot from SPI flash. If I use SPI_AP, then the boot mode as default can also boot success, it will not boot fail because of not SPI_HOST?        2、About SPI_AP, I can get form UM111107 that two SJA1110, one SJA1110 is controlled by another SJA1110, but I am not sure that: can I use S32G274A as an external microcontroller to control SJA1110 through SPI_AP？In this case NVM boot can still boot success from SPI flash？      Re: SJA1110 SPI_AP interface Hello @yangjinzhuang , SJA1110 supports NVM boot from external SPI flash or SDL boot from the host controller,  independently to usage of SPI_AP. Set DIP switch on your board accordingly to AN13185 chapter 3.2.1. You may also refer to UM11107 Software user manual for SJA1110 for more details. Both documents require Sign in. You need to use SPI_HAP_SS0_N to access all internal registers/settings by SPI_AP. SJA1110's SPI_PER is mostly used for cascading two SJA1110s. Best regards, Pavel

About entering IVOR1_Handler when using FlexCAN When I used multiple CAN channels of MPC5748G in FreeRTOS, in the execution FLEXCAN_DRV_RxFifo(INST_CANCOM2,&recvBuff); Or FLEXCAN_DRV_Receive(INST_CANCOM2,RX_MAILBOX2,&recvBuff); Until we have this problem: Enter into IVOR1_Vector: e_b IVOR1_Handler Part of the program is as follows: #if CAN1_EN FLEXCAN_DRV_Init(INST_CANCOM1, &canCom1_State, &canCom1_InitConfig0); //CAN0 FLEXCAN_DRV_ConfigRxMb(INST_CANCOM1, RX_MAILBOX, &RXdataInfo1, RX_MSG_ID); FLEXCAN_DRV_ConfigTxMb(INST_CANCOM1, TX_MAILBOX, &TXdataInfo1, TX_MSG_ID); if(! canCom1_InitConfig0.fd_enable) { FLEXCAN_DRV_ConfigRxFifo(INST_CANCOM1,FLEXCAN_RX_FIFO_ID_FORMAT_A,&RX_id_table1); } FLEXCAN_DRV_InstallEventCallback(INST_CANCOM1,CAN_CallBackHandle,NULL); if(canCom1_InitConfig0.fd_enable) { FLEXCAN_DRV_Receive(INST_CANCOM1,RX_MAILBOX,&recvBuff); } else { FLEXCAN_DRV_RxFifo(INST_CANCOM1,&recvBuff); } #endif #if CAN2_EN FLEXCAN_DRV_Init(INST_CANCOM2, &canCom2_State, &canCom2_InitConfig0); //CAN1 FLEXCAN_DRV_ConfigRxMb(INST_CANCOM2, RX_MAILBOX2, &RXdataInfo2, RX_MSG_ID); FLEXCAN_DRV_ConfigTxMb(INST_CANCOM2, TX_MAILBOX, &TXdataInfo2, TX_MSG_ID); if(! canCom2_InitConfig0.fd_enable) { FLEXCAN_DRV_ConfigRxFifo(INST_CANCOM2,FLEXCAN_RX_FIFO_ID_FORMAT_A,&RX_id_table2); } FLEXCAN_DRV_InstallEventCallback(INST_CANCOM2,CAN_CallBackHandle,NULL); if(canCom2_InitConfig0.fd_enable) { FLEXCAN_DRV_Receive(INST_CANCOM2,RX_MAILBOX2,&recvBuff); } else { FLEXCAN_DRV_RxFifo(INST_CANCOM2,&recvBuff); } MPC5748G-GW-RDB  回复： About entering IVOR1_Handler when using FlexCAN I have solved this problem by increasing the FreeRTOS heap size. This is done by increasing the size of configTOTAL_HEAP_SIZE in FreeRTOSConfig.h Re: About entering IVOR1_Handler when using FlexCAN Sure. Thank you very much for taking the time to help me troubleshooting the problem. My project is a collection of ENET and CAN project based on the sample program, if you want to execute to send the wrong place, may require you to complete the TCP connection. My test project looks like this: Re: About entering IVOR1_Handler when using FlexCAN Hi, can you share full simplified project, so it can be tested? BR, Petr

rte_kni.ko not found within the DPDK on Ubuntu 20.04 PC I am testing dpdk application in PC with PCI-E Dual-RJ45 gigabit NIC card to develop a network based application. I have started my project with dpdk 21.08 and Codewarrior IDE. PC details : uname -a Linux mglocadmin-ThinkCentre-M73 5.15.0-105-generic #115~20.04.1-Ubuntu SMP Mon Apr 15 17:33:04 UTC 2024 x86_64 x86_64 x86_64 GNU/Linux The following steps to install DPDK (Data Plane Development Kit) on Ubuntu 20.04: sudo apt update sudo apt install build-essential meson python3-pyelftools libnuma-dev pkgconf wget https://fast.dpdk.org/rel/dpdk-21.08.tar.xz tar -xf dpdk-21.08.tar.xz meson build ninja -C build meson -Dexamples=all build sudo ninja install sudo ldconfig Setup hugepage in PC: mkdir -p /dev/hugepages mountpoint -q /dev/hugepages || mount -t hugetlbfs nodev /dev/hugepages echo 1024 > /sys/devices/system/node/node0/hugepages/hugepages-2048kB/nr_hugepages Log "dpdk-devbind.py -s": Network devices using DPDK-compatible driver 0000:02:00.0 '82571EB/82571GB Gigabit Ethernet Controller D0/D1 (copper applications) 105e' drv=uio_pci_generic unused=e1000e,vfio-pci 0000:02:00.1 '82571EB/82571GB Gigabit Ethernet Controller D0/D1 (copper applications) 105e' drv=uio_pci_generic unused=e1000e,vfio-pci Network devices using kernel driver 0000:03:00.0 'RTL8111/8168/8411 PCI Express Gigabit Ethernet Controller 8168' if=enp3s0 drv=r8169 unused=vfio-pci,uio_pci_generic *Active* I follow the steps to load DPDK KNI Kernel Module below the link https://doc.dpdk.org/guides-21.08/prog_guide/kernel_nic_interface.html#kni-default-carrier-state Testing KNI application in PC $ sudo ./dpdk-kni -l 0-1 -n 4 -- -P -p 0x3 --config="(0,0,0),(1,1,1)" ERROR log: EAL: Detected 4 lcore(s) EAL: Detected 1 NUMA nodes EAL: Detected static linkage of DPDK EAL: Multi-process socket /var/run/dpdk/rte/mp_socket EAL: Selected IOVA mode 'PA' EAL: No available 1048576 kB hugepages reported EAL: VFIO support initialized EAL: Probe PCI driver: net_e1000_em (8086:105e) device: 0000:02:00.0 (socket 0) EAL: Probe PCI driver: net_e1000_em (8086:105e) device: 0000:02:00.1 (socket 0) TELEMETRY: No legacy callbacks, legacy socket not created KNI: Can not open /dev/kni APP: Initialising port 0 ... KNI: KNI subsystem has not been initialized. Invoke rte_kni_init() first EAL: Error - exiting with code: 1 Cause: Fail to create kni for port: 0 Try to find rte_kni.ko kernal module file in DPDK directory : $ sudo find / -name rte_kni.ko rte_kni.ko: No such file or directory NOTE: Dpdk-l2fwd and Dpdk-L2fwd-crypto working in PC kindly help us to resolve this issue. Re: rte_kni.ko not found within the DPDK on Ubuntu 20.04 PC Thank you for your Reply @yipingwang  . I am using meson to configuration and ninja to build DPDK application and also i find the solution on my own Here the solution(using Meson): 1.Need to edit the /home/mglocadmin/NIC/dpdk-21.08/meson_options.txt file and make sure that you enable the boolean as a true to get rte_kni.ko       option('enable_kmods', type: 'boolean', value: true, description:'build kernel modules') 2.Build and test KNI       meson -Dexamples=all build       ninja –C build Log: make: Entering directory '/usr/src/linux-headers-5.15.0-105-generic' CC [M] /home/mglocadmin/NIC/dpdk-21.08/build/kernel/linux/kni/kni_net.o CC [M] /home/mglocadmin/NIC/dpdk-21.08/build/kernel/linux/kni/kni_misc.o LD [M] /home/mglocadmin/NIC/dpdk-21.08/build/kernel/linux/kni/rte_kni.o MODPOST /home/mglocadmin/NIC/dpdk-21.08/build/kernel/linux/kni/Module.symvers CC [M] /home/mglocadmin/NIC/dpdk-21.08/build/kernel/linux/kni/rte_kni.mod.o LD [M] /home/mglocadmin/NIC/dpdk-21.08/build/kernel/linux/kni/rte_kni.ko BTF [M] /home/mglocadmin/NIC/dpdk-21.08/build/kernel/linux/kni/rte_kni.ko 3.Load KNI module sudo insmod /home/mglocadmin/NIC/dpdk-21.08/build/kernel/linux/kni/rte_kni.ko kthread_mode=multiple Re: rte_kni.ko not found within the DPDK on Ubuntu 20.04 PC To cross-compile DPDK, including the kernel modules, the kernel source tree needs to be specified by setting RTE_KERNELDIR: make -j CROSS=aarch64-linux-gnu- RTE_KERNELDIR= CROSS_COMPILE=aarch64-linux-gnu-

SPI Comm Between i.MX8MP MPU and MCU Hello, we are planning to read sensor data using an MCU and intend to utilize this data on our custom board equipped with an i.MX8MP. The data will be transferred from the MCU to the i.MX via SPI. My question is: should we use the M7 core on the i.MX to receive the data and then process it within our user application on our custom distro, or should we handle the SPI communication directly with the A core? Which method would be easier to integrate and result in lower latency? Re: SPI Comm Between i.MX8MP MPU and MCU Hello, Do you have any examples of this type of communication? For both sides, an MCU and an MPU? Thanks! Re: SPI Comm Between i.MX8MP MPU and MCU There is latency using rpmsg, the m7 write data to shared memory(need time), then use MU to notify A core(need time), then A core read data from shared memory(need time). So why not receive data from A core SPI directly as you need lower latency Re: SPI Comm Between i.MX8MP MPU and MCU We'll have to write a driver to parse the incoming data to use in the userspace. Any suggestions for this purpose or do you see any limitations? Also Why using m7 core and using the sensor data on the user space via rpmsg is a bad idea? Thanks! Re: SPI Comm Between i.MX8MP MPU and MCU Hi @Wobaffet   Which method would be easier to integrate and result in lower latency? --> I think use it in A core is better for you.

KEA128 UART Bootloader 你好，我在KEA128单片机开发遇到一个问题，这个问题通过Jlink烧写程序调试是完全没有问题的，但是当我通过bootloader下载该程序，出现主程序死机的情况。 当我使用以下该程序（设置占空比）时，通过bootloader下载之后，程序出现死机现象。当我把该函数的内容注释掉，则一切正常。这种情况Jlink烧写是完全没有问题的，这个问题让我无从下手，希望能得到帮助，告诉我应该往那个方向寻找答案。 void heater_output(uint32 duty) { if(heater_switch==on) { ftm_pwm_duty(ftm0,ftm_ch0,duty);//设置占空比 } else { heater_pwm_duty=0; ftm_pwm_duty(ftm0,ftm_ch0,0); } } 这是我的跳转程序 void bootup_application(uint32_t appEntry, uint32_t appStack) { static void (*jump_to_application)(void); static uint32_t stack_pointer; //shutdown_drivers(); jump_to_application = (void (*)(void))appEntry;//跳转APP入口地址 stack_pointer = appStack; //堆栈指针 // SCB->VTOR = appEntry; __set_MSP(appStack); //设置主程序堆栈指针 __set_PSP(appStack); //设置进程堆栈指针 jump_to_application(); //跳转 } Re: KEA128 UART Bootloader Hi, 建议您考虑S32K系列， 它是车规级芯片。 https://www.nxp.com/products/processors-and-microcontrollers/s32-automotive-platform/s32k-auto-general-purpose-mcus:S32K-MCUS 如果你老师进入hardFault, 请看看stack是否分配小了。 BR XiangJun Rong Re: KEA128 UART Bootloader 你好，谢谢您的回复，我通过不下载仿真调试发现总是进入HardFault_Handler函数，我觉得可能是调用层次比较深，然后再主循环里直接调用设置占空比的函数，结果没有出现卡死情况。请问这种情况在这款芯片常见吗，我的APP程序大概33K左右，从0x8000开始，如果我想在项目中选择性能更好的性价比的车规级芯片，能运行更多算法，我应该如何选择。 Re: KEA128 UART Bootloader Hi, 那你把appEntry加上1. BR XiangJun Rong Re: KEA128 UART Bootloader 你好，当我把这行代码放进去，出现一个错误，（jump_to_application =jump_to_application +1；）使用的是IAR软件编译器，报错信息为，Error[Pe852]: expression must be a pointer to a complete object type 。这个该如何解决呀？ Re: KEA128 UART Bootloader Hi, 请使用下列代码： //shutdown_drivers(); jump_to_application = (void (*)(void))appEntry;//跳转APP入口地址 jump_to_application =jump_to_application +1； stack_pointer = appStack; //堆栈指针 // SCB->VTOR = appEntry; __set_MSP(appStack); //设置主程序堆栈指针 __set_PSP(appStack); //设置进程堆栈指针 jump_to_application(); //跳转 因为是thumb指令集， 请试一下，看行不行 BR XiangJunRong

Control GPIO using libgpiod API Hello, I'm using IMX8ULP EVK9 board and i have onboard LED. I'm able to control LED using "gpioset -c /dev/gpiochip4 20=1" command. Now I'm trying to control LED using C code but on that time i'm getting "Request lines failed: Invalid argument" error. I'm using libgpiod 2.0. Following is my C code const char *chipname = "/dev/gpiochip4"; unsigned int line_num = 20; struct gpiod_chip *chip; struct gpiod_request_config *req_cfg; struct gpiod_line_config *line_cfg; struct gpiod_line_request *request; // Open the GPIO chip chip = gpiod_chip_open(chipname); if (!chip) { perror("Open chip failed"); return 1; } // Allocate and configure the request config req_cfg = gpiod_request_config_new(); gpiod_request_config_set_consumer(req_cfg, "led_control"); // Allocate line config line_cfg = gpiod_line_config_new(); // Request the line unsigned int offsets[] = {line_num}; request = gpiod_chip_request_lines(chip, req_cfg, line_cfg); if (!request) { perror("Request lines failed"); gpiod_chip_close(chip); return 1; } // Blink the LED for (int i = 0; i < 10; i++) { gpiod_line_request_set_value(request, line_num, GPIOD_LINE_VALUE_ACTIVE); // Turn on LED sleep(1); gpiod_line_request_set_value(request, line_num, GPIOD_LINE_VALUE_INACTIVE); // Turn off LED sleep(1); } // Clean up gpiod_line_request_release(request); gpiod_request_config_free(req_cfg); gpiod_line_config_free(line_cfg); // Free line_cfg gpiod_chip_close(chip); i.MX8ULP Re: Control GPIO using libgpiod API Hi @Zhiming_Liu ,                       I'm trying to read GPIO line values in imx91  using libgpiod by c application. But showing gpiod.h is not found. I installed libgpiod-tools and able to see gpiod.h in /usr/include/. But when I compile recipe it is showing error undefined reference to API used. It is linking error is there any way to read value of GPIO using C application. Thanks Re: Control GPIO using libgpiod API Hello, Please refer libgpiod 2.0 examples to modify your code. https://github.com/brgl/libgpiod/tree/v2.2.x/examples Best Regards, Zhiming

UART- S32K144 EVB I am currently working with the S32K144-EVB and attempting to perform data transmission and reception using UART. However, I am encountering difficulties with the UART configuration, especially since I am new to S32Design Studio. Initially, I tried the example UART project and successfully received the transmitted value. However, when I created a new project and configured the UART, I did not receive any data. Could you please provide guidance on how to properly configure UART in a new project. Re: UART- S32K144 EVB Hi @DIVYAJ1, Sorry for the misunderstanding, but are you using config tools or are you configuring the drivers yourself with registers? Following the thread, I was giving recommendations on how to configure the UART by using the GUI for the drivers, but the project you shared does not use these generated configurations. If you need to configure the example in bare metal, please follow AN5413: S32K1xx Series Cookbook, which includes an example for a simple UART 9600 baud transfer to a COM port on a PC in chapter 2.7. Best regards, Julián Re: UART- S32K144 EVB Here is the project file; Re: UART- S32K144 EVB Hi @DIVYAJ1, Could you share your code (main.c)? Maybe you are missing some steps initializing or using the functions. The basic uart project should look something like this: int main(void) { /* Initialize and configure clocks * - see clock manager component for details */ CLOCK_SYS_Init(g_clockManConfigsArr, CLOCK_MANAGER_CONFIG_CNT, g_clockManCallbacksArr, CLOCK_MANAGER_CALLBACK_CNT); CLOCK_SYS_UpdateConfiguration(0U, CLOCK_MANAGER_POLICY_AGREEMENT); /* Initialize pins * - See PinSettings component for more info */ PINS_DRV_Init(NUM_OF_CONFIGURED_PINS0, g_pin_mux_InitConfigArr0); /* Initialize for UART_PAL */ UART_Init(&uart_instance, UART_PAL_CONFIG); /* Send a welcome message */ UART_SendDataBlocking(&uart_instance, (uint8_t *)welcomeMsg, strlen(welcomeMsg), TIMEOUT); } Best regards, Julián Re: UART- S32K144 EVB Hi, Thankyou for replying. I imported the file you provided and successfully received transmitted data in the debug terminal. However, after following the UART configuration steps to create a new project, I am only seeing ‘NULL’ in the debug terminal instead of the expected transmitted data. Re: UART- S32K144 EVB Hi @DIVYAJ1, In order to use UART, you can simply add the UART component and configure the pins through Config Tools:         If you want to use interrupts or a callback for your reception and transmission, then the IntCtrl driver must also be added, but for a simple uart configuration that should be enough. I've attached a simple example which echoes the inputs through a serial terminal through UART1 (connected to the EVB's USB): Best regards, Julián

Issue on Tresos tool for I2c configuration - S32K344uC Hello all, I'm facing a issue when configure I2C on Tresos tool for S32K344 microcontroller. The current version that I'm using is: 4.0.0 HF02_D2407 (the latest version). I configured the I2c as Fast mode, but when I try to generate the code, I get this error: Can anyone help me with this problem? I'm not using the HighSpeedMode, so why there is this error? Thank you, MVR Re: Issue on Tresos tool for I2c configuration - S32K344uC Since you don't really need to use LPI2C_HIGHSPEED_MODE, you only need to modify the configuration so that I2cDataValidDelay meets the restrictions. Re: Issue on Tresos tool for I2c configuration - S32K344uC Hello @Robin_Shen , I did it, but I continue getting error: Where should I recalculate this baudarte? I tried in the "Master Configuration" tab.  Re: Issue on Tresos tool for I2c configuration - S32K344uC Hi Sorry for the inconvenience we bring you! The issue is that the I2c Baud Rate field from I2cHighSpeedModeConfiguration container needs to be updated after I2c Prescaler field is updated, To fix this field, I2c Operating Mode should be set on LPI2C_HIGHSPEED_MODE and recalculate the I2c Baud Rate from this container. After I2c Baud Rate field is recalculated, I2c Operating Mode field should be switch on the desired operating mode. Best Regards, Robin ------------------------------------------------------------------------------- Note: - If this post answers your question, please click the "Mark Correct" button. Thank you! - We are following threads for 7 weeks after the last post, later replies are ignored Please open a new thread and refer to the closed one, if you have a related question at a later point in time. -------------------------------------------------------------------------------

Does i.MX 6 support LPDDR2-1066 channels? We are using MCIMX6Q6AVT10AD. So far I got a question about LPDDR2 memory interface frequency.   According to IMX6DQRM.pdf,  "i.MX 6Dual/6Quad Applications Processor Reference Manual" (Rev. 6, 05/2020), Chapter "1.4 Features", the SoC supports 1/2 LPDDR2-1066 channels.   But according to another document, IMX6DQAEC.pdf, "i.MX 6Dual/6Quad Automotive and Infotainment..." , Data Sheet (Rev. 6, 11/2018), Chapter "1.2 Features", it only supports  1/2 LPDDR2-800 channels.   Could you clarify it, please? i.MX6 All i.MX6Quad Re: Does i.MX 6 support LPDDR2-1066 channels? Hello, That is a typo in documentation. i.MX6 supports 1/2 LPDDR2-800 channels. Best regards.

S32DS can't install freertos for S32K344 Hi everyone, What I saw a post just now is the same as my subject. when I install the offline installation package, I also found I can't install freertos, reporting one or more required tiems could not be found. image as follows: it show that I had installed the software., nstallation details as follows:  but I can't create new freertos project from k3 example, images as follows: how do I install successfully? Re: S32DS can't install freertos for S32K344 Thanks, it's done! Re: S32DS can't install freertos for S32K344 Hi @Hanoch  The FreeRTOS version 2.0.3 was developed for S32DS v3.4 using S32K3 Real-Time Drivers AUTOSAR 4.4 Version 2.0.3. According to the provided information, you are using S32DS v3.5 and RTD v3.0.0; the FreeRTOS version compatible with this SW is the 3.1.0 (SW32K3_FreeRTOS_10.5.1_3.1.0_D2304). B.R. VaneB

S32K1XX BOOTLODER Hello, team.     I'm currently developing the bootloader for S32K146, but I'm encountering some issues when writing data to the flash. I'd appreciate it if you could offer some advice. As shown in the image, this is an SREC file generated by S32DS IDE. However, I noticed a discontinuity in the addresses in this file: 0xA7260 ------- 0xA7270 ------- 0x7274. The remaining addresses are incremented by "0x10", but there is a gap between 0xA7270 and 0xA7274 where the increment is only 0x4. This issue prevents me from writing data to the flash because each flash write operation must occupy at least 8 bytes. However, there is only a 4-byte space provided here, making it impossible to write to the flash.    This is the problem I'm facing, and I hope you can suggest some solutions. Thank you. 回复： S32K1XX BOOTLODER Hi @shiqi_seventeen  Yes, that's correct. The minimum amount you can program is one phrase - 8 bytes: The best solution for bootloaders is to align the s-record file. Take a look at this thread for details: https://community.nxp.com/t5/S32-Design-Studio/Why-does-the-AN12218SW-bootloader-fails-to-parse-the-generated/td-p/1275665 Regards, Lukas 回复： S32K1XX BOOTLODER Could you please help me confirm whether the data written to the flash of S32K146 must be at least 8 bytes?

S32DS can't build freertos for S32K312 hi everyone When using 'SW32K3_FreeRTOS_10_5_1_UOS_3_1_0_DS_updatesite_D2304', generate routine for S32K312, compile fails.and where to download template software for S32K312EVK Re: S32DS can't build freertos for S32K312 Hi Select the "S32 Configuration Tool" menu then click on the desired configuration tool (Pins, Cocks, Peripherals etc...). Clicking on any one of those will generate all the components. Make the desired changes(if any) then click on the "S32 Configuration Tool->Update Code" button. Do you still encounter errors when you build after clicking Update Code? I refer to HOWTO: offline install S32K3 RTD 3.0.0 in S32DS v3.5 to install S32K3, and then install SW32K3_FreeRTOS_10_5_1_UOS_3_1_0_DS_updatesite_D2304.zip. No errors will be encountered when building. Sorry, I haven't seen the S32K312 examples since the version after S32K3 RTD 2.0.3. As you know, S32K3 has many derivatives, so to reduce effort, in the most recent RTD releases we only provide examples for K344, K358, and K396. Best Regards, Robin ------------------------------------------------------------------------------- Note: - If this post answers your question, please click the "Mark Correct" button. Thank you! - We are following threads for 7 weeks after the last post, later replies are ignored Please open a new thread and refer to the closed one, if you have a related question at a later point in time. -------------------------------------------------------------------------------

SPI communication with FXIO I encountered two problems in configuring FXIO for SPI communication with S32K312: 1. The baud rate configured by EB is 100KHz, but according to the measurement results, it is actually 200K. What's going on? 2. The configuration of the three parameters Cs2Cs, Clk2Cs and Cs2Clk in EB seems to be invalid for FXIO. What's going on? The following are screenshots of the configuration and test results. Re: SPI communication with FXIO Yes，clock config is Option-B.I have found the answer in the latest version of the update record. It should be that there is a problem with the clock source selected when calculating the baud rate.Thinks！ Re: SPI communication with FXIO Hello @WeiCh, 1. Is the system clock set precisely to one of the clock options listed in the RM? For example:  152. Option B - Reduced Speed mode (CORE_CLK @ 120 MHz) 2. This is a HW feature of the LPSPI module. Regards, Daniel

fs23 Lin mode swith question Hello, We encountered a question while debugging the FS LIN functionality. Specifically, we found that in debug mode, we cannot set the LINTRCV_FS23_TRCVMODE_OFF mode using the LinTrcv_fs23_SetMode() function. The code snippet is as follows: Std_ReturnType LinTrcv_fs23_SetMode(uint8 u8LinNetwork, LinTrcv_fs23_TrcvModeType eOpMode) { uint16 u16RegData = 0U; Std_ReturnType eStatus; LinTrcv_fs23_TrcvModeType eNewHwOpMode = LINTRCV_FS23_TRCVMODE_INVALID; /* Read M_LIN register. */ eStatus = Sbc_fs23_ReadRegister(SBC_FS23_M_LIN_ADDR, &u16RegData); if ((Std_ReturnType)E_OK == eStatus) { /* Set new register value. */ u16RegData &= ~(SBC_FS23_M_LIN_MODE_MASK | SBC_FS23_M_LIN_SLOPE_MASK| SBC_FS23_M_LIN_FS_DIS_MASK); if(TRUE == xG_drivers[u8LinNetwork].bLinSlowSlope) { u16RegData |= SBC_FS23_M_LIN_SLOPE_SLOW; } if(FALSE == xG_drivers[u8LinNetwork].bLinFailsafeDisable) { u16RegData |= SBC_FS23_M_LIN_FS_DIS_KEEP; } u16RegData |= ((uint16)eOpMode << SBC_FS23_M_LIN_MODE_SHIFT); eStatus = Sbc_fs23_WriteRegister(SBC_FS23_M_LIN_ADDR, u16RegData); .... /*Check the real hardware state*/ eStatus |= LinTrcv_fs23_GetMode(u8LinNetwork, &eNewHwOpMode); if((eNewHwOpMode == eOpMode) && ((Std_ReturnType)E_OK == eStatus)) { eStatus = (Std_ReturnType)E_OK; } else { eStatus = (Std_ReturnType)E_NOT_OK; } } return eStatus; } The eOpMode is LINTRCV_FS23_TRCVMODE_OFF,  the eNewHwOpMode  is LINTRCV_FS23_TRCVMODE_NORMAL. The manual states that in debug mode, LIN defaults to active mode. Is this behavior normal? Thanks! Re: fs23 Lin mode swith question Hi @gumu , I got confirmation from hardware team that it's a normal behaviour. In debug mode, the transceiver mode is forced ACTIVE. So even if you try and change the LIN_MODE field to OFFLINE (OFF, 2b00) then the transceiver stays in active mode. Re: fs23 Lin mode swith question Hi, I have to check with hardware team. Can you please let me know what version of FS23 that you have? Or what is the part number? Re: fs23 Lin mode swith question Hi Quang (@quangvuanh), Could you please help with this question from Anhui Zhitu Technology China? Thanks & BRs, Tomas

より大きなシステムの一部としてのNNモデル - eIQ、Glowによるビルドプロセス こんにちは、eIQ + Glowなどのサードパーティベンダーの最適化により、複雑なシステムをAIモデルで強化することはどのように可能になるのか疑問に思います。私が理解した限りでは、これらは*推論*中にモデルとCPUの使用率を最適化するだけです。精度を達成するために必要な残りのモジュール、たとえば、データの前処理、特徴エンジニアリングは、グロービルドにこれらのステップを含める必要がある場合、手書きの方法でC言語で個別に記述する必要があります。では、これらの前処理ステップには最適化はありませんよね? さらに大局的に見ると、おそらくすでに独自のビルドプロセスを持っている複雑なシステムでは、Glow eccからHWへの最適化を活用できませんよね?「複雑な」システム全体に対して 1 つのビルド プロセスのみが存在する必要があります。

Where can I find it?S32_SDK_S32K1xx_RTM_4.0.3 Downloading S32_SDK_S32K1xx_RTM_4.0.3 in s32ds will give an error,If downloaded offline, S32_SDK_S32K1xx_RTM_4.0.3 cannot be found in the official website Re: Where can I find it?S32_SDK_S32K1xx_RTM_4.0.3 Some companies' IT restricts http access, so it is recommended to change Available S32DS Software Sites to https. Re: Where can I find it?S32_SDK_S32K1xx_RTM_4.0.3 So now I have returned s32ds 3.4, but can not find S32_SDK_S32K1xx_RTM_4.0.3 Re: Where can I find it?S32_SDK_S32K1xx_RTM_4.0.3 Do not use S32K1 SDK with S32DS v3.5. According to the currently available information, we don’t have any plan to integrate S32SDK S32K1XX 4.0.3 into S32DS 3.5 or above version. Re: Where can I find it?S32_SDK_S32K1xx_RTM_4.0.3 I want to open the project created by old version s32ds3.4+S32_SDK_S32K1xx_RTM_4.0.3, I tried s32ds 3.5 does not work with old version project Re: Where can I find it?S32_SDK_S32K1xx_RTM_4.0.3  Extensions and Updates install the S32 SDK for S32K1xx RTM 4.0.3 in S32DS 3.4.Prompts installation failure, like the first image，S32K1xx development package only S32K1 SDK 4.0.2，There is no S32 SDK for S32K1xx RTM 4.0.3 Re: Where can I find it?S32_SDK_S32K1xx_RTM_4.0.3 Hi You should be able to use Extensions and Updates install the S32 SDK for S32K1xx RTM 4.0.3 in S32DS 3.4. If the online installation fails, please install the S32K1xx development package first, and then install S32SDK S32K1XX RTM 4.0.3.  Sorry, there is no offline installation package for S32K1 SDK 4.0.3. By the way, it is recommended to install the latest S32K1 RTD 2.0.x by refer to HOWTO: offline install S32K1 RTD 2.0.0 in S32DS v3.5   Best Regards, Robin ------------------------------------------------------------------------------- Note: - If this post answers your question, please click the "ACCEPT AS SOLUTION" button. Thank you! - We are following threads for 7 weeks after the last post, later replies are ignored Please open a new thread and refer to the closed one, if you have a related question at a later point in time. -------------------------------------------------------------------------------

K32W061/JN5189: Thread support for ‘Enhanced Frame Pending' (EFP)? Which version of Thread is supported by the current NXP SDK (v2.6.13)? I'm asking because we want to use the Enhanced Frame Pending (EFP) feature introduced in Thread v1.2. If already supported by the SDK, then how do we activate this feature? Re: K32W061/JN5189: Thread support for ‘Enhanced Frame Pending' (EFP)? Hello, Hope you are doing well. The OpenThread middleware is not included on the SDK. You need to get it from the GitHub - NXP/ot-nxp: OpenThread on NXP examples. Please check the information of each release directly: Releases · NXP/ot-nxp · GitHub Regards, Ricardo