HI Dear
I set FS32K144WAT0WLFT PTD3 to ADC, will lead mcu to hardfault.
I've encountered this issue with the 146 before—could you check it out for me?
I have never encountered a hardfault on the MCU caused by selecting PTD3 as ALT0 (ADC1_SE3). Regarding hardfault, I recommend reading: Fault handling on S32K14x. Or tell me which line of the function triggers the hardfault during debugging.
I have checked the schematic you attached:
Debug and programing interface:
Please read section "4 Debug and programing interface" of AN5426 Hardware Design Guidelines for S32K1xx Microcontrollers (Rev. 6 December, 2021).pdf:
For PTC4 (SWD_CLK), an external pull-down resistor is recommended rather than a pull-up resistor.
Clock circuitry:
I can't comment on the XTAL circuit, the Rs and load capacitors values are dependent on the specifications of the crystal and on the board capacitance. It is recommended the customer develops evaluation and characterization of the crystal on their PCB with the part manufacturer.
However, the resistance value (470Ω) of R44 (Series resistor for current limitation) shown in your screenshot appears to be on the high side.
Please refer to the section "3.2 Suggestions for the PCB layout of oscillator circuit" of AN5426 Hardware Design Guidelines for S32K1xx Microcontrollers (Rev. 6 December, 2021).pdf.
In the S32K1xx datasheet, you can find min. required Vpp at EXTAL (Table 27. External System Oscillator electrical specifications), so I would recommend measuring it. Also, you need to ensure gmXOSC > 5 * gm_crit.
Regarding feedback resistor for oscillator, it can be eliminated if SOSC is used at "low-gain" mode (SCG_SOSCCFG[HGO]=0). It's customer's choice which they want, lower power consumption (HGO=0) or higher noise immunity (HGO=1). Need to populate feedback resistor when SOSC is used at HGO=1 high-gain mode.
ADC:
The ADC input voltage range (VADIN) should be between VREFL and VREFH.
Hi Robin
PTD3 selected ALT0 (ADC1_SE3), Have you ever encountered a situation like this, which causes the MCU to enter Hardfault
Thanks!
Hi
Sorry, I didn't understand why you attached the schematic.
Could you clarify whether you selected ALT0 (ADC1_SE3) or ALT7 (NMI_b) for the PORT_PCR[MUX] setting of PTD3?
Best Regards,
Robin