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S32K142 LPSPI0 Master (lpspi_transfer example): SCK clock not toggling correctly

Hello NXP Community,

I am using the NXP lpspi_transfer_s32k142 example with LPSPI0 in Master mode on an S32K142 board, without major changes to the example configuration.

My issue is that the SCK/Clock waveform is not toggling correctly. I am monitoring SCK, MOSI, MISO and PCS with a logic analyzer.

For an 8-bit (1-byte) transfer, I expect 8 SCK clock pulses, but the logic analyzer shows an abnormal/continuous-looking clock waveform instead of the expected pulses.

Configuration:

• LPSPI0 – Master
• 500 kHz
• 8-bit frame
• PCS0
• CPOL = Active High
• CPHA = 1st edge
• Transfer type = Interrupt

I have attached the logic analyzer screenshot showing the SCK waveform.

Could someone please help me understand why the SCK clock is not toggling correctly in the NXP example and what configuration I should check?

Thank you.

Re: S32K142 LPSPI0 Master (lpspi_transfer example): SCK clock not toggling correctly

If possible, I suggest you send me the modified test project so that I can quickly reproduce the problem you encountered on the S32K142EVB.

Re: S32K142 LPSPI0 Master (lpspi_transfer example): SCK clock not toggling correctly

Hi Robin,

Thank you for your response.

In my current configuration, PCS continuous is unchecked, and the generated configuration has:

.isPcsContinuous = false

I have not modified this setting.

In the uploaded waveform, I am also not getting the expected clean SPI timing. For a 1-byte transfer, I expect 8 SCK clock pulses while PCS is asserted for the complete transfer (PCS active → 8 clock pulses → PCS inactive). However, my logic analyzer capture does not show this expected behavior clearly. The SCK pulses appear irregular, and the PCS/Enable signal is not showing the expected high/low behavior around the complete SPI frame.

I have attached the current waveform for reference.

Could you please confirm whether this PCS and SCK behavior is expected with the LPSPI_DRV_MasterTransferBlocking() API and the current LPSPI configuration?

I will also test with PCS continuous enabled and share the result.

Regards,
Resham

Re: S32K142 LPSPI0 Master (lpspi_transfer example): SCK clock not toggling correctly

Hi

The image you uploaded is too blurry; I can't see the SPI waveform clearly.

Did you modify the LPSPI0 configuration of lpspi_transfer_s32k142 to select PCS continuous?

lpspi_transfer_s32k142 LPSPI0 PCS continuous.pnglpspi_transfer_s32k142 LPSPI0 PCS continuous.pnglpspi_transfer_s32k142 LPSPI0 PCS continuous.png

It is recommended to use arrows or text to mark where you think there is a problem on a clear SPI waveform. This will help me quickly understand your question.

Best Regards,
Robin

Re: S32K142 LPSPI0 Master (lpspi_transfer example): SCK clock not toggling correctly

Hi,

Please find attached the ZIP file containing the modified LPSPI transfer test project for the S32K142EVB.

Could you please check the project and let me know if the LPSPI transfer configuration is correct or if any changes are required?

Thanks for your support.

Best regards,
Resham