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Accessing SEMA42 unit on main platform domain from two different cortex M7 in S32K5

I am trying to access SEMA42_1 unit on main platform from two different cortex M7 cores (M7_0 and M7_1) in S32K5. The system hangs up. I cannot share the inhouse workspace here.

The errata ERR053433 states: SEMA42: Simultaneous access to SEMA42_0 and PBRIDGE_2 by more than one application core causes the system to hang.

Unfortunately the workaround of using SEMA42_1 does not fix the system hang issue.

Can you configure and verify two cortex M-7 cores on S32K56x and have them access gate0 of the SEMA42_1 unit on your Design studio and enable the optimization -Os.

The system hang issue goes away by using any ONE of the following,

Disable optimisations -O0
Disable Instruction cache
Use SRAM of another domain on the SoC e.g. CPE
Stepping in via debugger

Re: Accessing SEMA42 unit on main platform domain from two different cortex M7 in S32K5

Hello @seasonedbit,

As you may know, S32K5 is currently in a preproduction phase; Enablement (documentation, software, and boards) are available for approved customers only, and thus is not supported by our global online support team yet.

Could you please contact your FAE or assigned NXP contact who provided the device in the first place? They will be able to provide further support.

Thank you for your understanding.

Best regards,
Julián