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2380304_ja-JP
2380304_ja-JP
少し前に質問をしました - https://community.nxp.com/t5/S32K/Understanding-Atomics-ie-STREX-LDREX-on-S32K3/mp/2356118 - 回答では、チェック対象のメモリがSRAMにある場合、ISR/IRQなどがメインスレッドと競合するのを防ぐために、LDREX/STREX/CLREXをシングルコアでのみ使用している場合でも、その動作に頼ることはできないと示唆しているように思えました。
テストを行った結果、期待通りに動作しているようです。LDREX/STREX/CLREXは単一コアからのアクセスを競合しないように設計されている、という点について設計チームから確認をいただけますでしょうか？DMAとCortex-M7コア間の排他的アクセスのようなものを防ぐことはできないと分かっていますが、コア自身との排他的アクセスはどうでしょうか？
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