Understanding Atomics (i.e. STREX/LDREX) on S32K3

[kscz]

Chapter 17 of the S32K3XX reference manual says that "S32K3 does not support the ARM load- and store- exclusive instructions."

But the Errata calls out the use of LDREX/STREX:

 are LDREX/STREX usable on the S32K344? Are they safe to use?

[db16122]

it seems the ERR050727 appears at MCXE315_MCXE316_0P98C but not on S32K related document?

[kscz]

The screenshot is from the document S32K3X4-0P55A-1P55A-ERRATA which I downloaded from https://www.nxp.com/products/S32K3. I assume it is generic errata for all cortex-M7 products so it may not actually imply anything useful for the S32K344 at all.

I would like clarification on what the quoted bit from chapter 17 of the reference manual means: "S32K3 does not support the ARM load- and store- exclusive instructions."

I've tested and LDREX/STREX don't appear to cause any sort of panic and appear to function as I would expect, but I assume there are subtleties I don't understand from my cursory explanation.

[danielmartynek · Accepted solution]

Hello @kscz,

Edited:

The Reference Manual, specifically Section 17.1.1, is somewhat misleading.
The LDREX and STREX instructions are supported on S32K3xx; however:

1. These instructions do not operate as global monitors, so they cannot be used for synchronization between multiple cores.
   Instead, a different mechanism must be used, for example SEMA42. 
2. These instructions can be used locally between two tasks running on the same core.

BR, Daniel

[kscz]

What does "not implemented on the S32K3xx device family" mean? They are not optional features for a cortex-M7 core. The instructions appear to both work (i.e. they do not cause a fault) and do what I expect them to do. Is there something about them which doesn't work?

I know they certainly won't work in a multi-core environment, but will the have the correct behavior in a single-core or a lockstep dual-core environment?

[danielmartynek]

Hi @kscz,

I edited my answer from yesterday after a discussion with the design team.
I will ask the responsible team whether this can be clarified in the Reference Manual.

Regards,

Daniel