Introduction
In the previous installment, as the first part of our exploration of SPI communication, we used two FRDM boards to run a sample SPI communication application.
This time, we will try changing the settings for four different SPI modes and check the actual SPI signals that are sent and received. This article assumes that you have completed the steps in the following [Part 1] article.
[Part 1] Let's run a sample application for SPI communication.
[Part 2] We will observe the actual SPI signals while changing the SPI mode and see how they change.
(Estimated time: 20 minutes) *Assumes that the content of the first part (MCUXpresso for VSC, SDK installed, and SPI application operation confirmed) has been completed.
table of contents
- Things to prepare
- SPI mode
- Check the CPOL and CPHA settings (Where are they configured in the sample code?)
- Actually verifying the SPI signal
- Measurement results of signals in each SPI mode
- In conclusion
1. Things to prepare
hardware
FRDM-MCXN947 (USB cable included) x 2
• Jumper wires: Multiple wires
• Logic analyzer (for SPI signal analysis)
software
SDK for FRDM-MCXN947
* SDK for MCX N947 (ver. This explanation assumes that version 26.3.0) has been installed in VS Code.
For instructions on setting up the development environment (MCUXpresso for VSC) and installing the SDK, please refer to the following article.
Article: Installing MCUXpresso for VSC and SDK (Japanese Blog)
2. SPI mode
The article "SPI Bus Overview" (Japanese blog) explains that there are a total of four modes, based on the combinations of CPOL = 0 or 1 and CPHA = 0 or 1.
- CPOL (Clock Polarity) : This setting determines which voltage level the clock line (SCLK) is at during "idle time" (when no communication is taking place).
- CPOL=0: Low during idle
- CPOL=1: High during idle
- CPHA (Clock Phase) : Sets whether the data transmission and latch (sampling) timing are aligned with the clock edge (rising or falling edge).
- CPHA=0: Data is sampled on the first clock edge, and output on the second.
- CPHA=1: Output data on the first clock edge, sample data on the second.
Table 1: Four modes and CPOL, CPHA
| CPOL | CPHA | |
| mode=0 | 0 | 0 |
| mode=1 | 0 | 1 |
| mode=2 | 1 | 0 |
| mode=3 | 1 | 1 |
Figure 1: Behavior based on CPOL and CPHA settings
3. Check the CPOL and CPHA settings (Where are they configured in the sample code?)
First, before examining the waveforms, I built and ran the SPI communication sample application from last time using its default settings. I will now check the default CPOL and CPHA settings.
CPOL and CPHA are defined in fsl_lspi.h .
Figure 2. Definitions of CPOL and CPHA ( fsl_lspi.h )
Next, the SPI initialization was performed within LPSPI_MasterGetDefaultConfig() in fsl_lpspi.c .
In the red box in the diagram below, we can see that CPOL=0 and CPHA=0 are set on the controller (master) side. The same file also contains the device (slave) side settings LPSPI_SlaveGetDefaultConfig() , so we will test by changing the CPOL and CPHA parameters in both the master and slave sides.
Figure 3 Master side setting location LPSPI_MasterGetDefaultConfig()
Figure 4. Slave-side configuration location: LPSPI_SlaveGetDefaultConfig()
4. Actually verify the SPI signal.
Now, referring to the "previous article," connect the two FRDM boards to your PC , open two serial monitors , and verify that the sample applications on each board are running .
Figure 5 SPI communication results on the serial monitor
In this state, connect the SPI terminals of the two FRDM boards.
*Please note that if you connect the wires first and then power on the FRDM board, it may not function correctly.
This is the same content as the previous article, but if you look at the circuit diagram of the FRDM-MCXN947, you will see that #8 of the J2 connector is MOSI and #10 is MISO.
Figure 6 SPI circuit diagram of FRDM-MCXN947
Connect the J2 connectors on the FRDM-MCXN947 with jumper wires as shown below.
*Please connect pins #6 and #8 of J2 in a crossed manner.
Table 2 SPI connection between FRDM-MCXN947
| LPSPI_master | LPSPI_slave |
| J2-14: GND | J2-14: GND |
| J2-12: CLK | J2-12: CLK |
| J2-6: SOUT(MOSI) | J2-8: SIN(MISO) |
| J2-8: SIN(MISO) | J2-6: SOUT(MOSI) |
| J2-6: SS(PCS) | J2-6: SS(PCS) |
These are the terminals corresponding to D10, D11, D12, and D13, which are typically used for SPI on Arduino shield sockets.
Figure 7 SPI Connection Diagram
*This time, we will connect a logic analyzer to check the signal between the Master and Slave.
Now, let's actually send and receive SPI signals to check if the logic analyzer is working correctly.
Figure 8 shows the results of SPI data transmission and reception displayed on the serial monitor.
Figure 9 shows the results of displaying SPI data transmission and reception using a logic analyzer.
Although the text in the image above is small, we were able to confirm that both transmission and reception were working correctly from the Master's perspective.
Looking at the transmission section (upper half of the image above), we can see that MOSI (Master Out Slave In) is incrementing, while MISO (Master In Slave Out) remains "High (=hFF)". Conversely, looking at the reception section (lower half of the image above), MOSI is fixed at "High (=hFF)", while MISO is incrementing.
This is the correct behavior, as explained in the SPI bus overview (Japanese blog) , the MOSI and MISO outputs are in a high-impedance state when not transferring data.
Now let's look at some actual signals.
5. Measurement results of signals in each SPI mode
From here, referring to section 3, "Checking CPOL and CPHA settings (Where are they set in the sample code?)" , we performed the following steps on both the master and slave: "Change the CPOL and CPHA values → Build → Write" and then conducted measurements.
SPI Mode 0: SPI signal with CPOL=0, CPHA=0 (default setting)
Figure 10: Data transmission waveform from Master to Slave when CPOL=0 and CPHA=0.
As can be seen in Figure 10, the clock (CLK) is low before data is transferred (idle) (orange box in the figure) , so we can see that POL = 0 .
Furthermore, the MOSI data is latched on the rising edge of the first CLK (red line in the figure) , and the MOSI data is changed on the falling edge of the second CLK (green line in the figure) , so we can see that CPHA = 0 .
SPI Mode 1: SPI signal with CPOL=0, CPHA=1
Figure 11: Data transmission waveform from Master to Slave when CPOL=0 and CPHA=1.
As can be seen in Figure 11 , CLK is low before data is transferred (idle) (orange box in the figure) , so we can see that POL = 0 .
In this case, the MOSI data is changed on the rising edge of the first CLK (green line in the figure) , and the MOSI data is latched on the falling edge of the second CLK (red line in the figure) , so we can see that CPHA = 1 .
SPI Mode 2: SPI signal with CPOL=1, CPHA=0
Figure 12: Data transmission waveform from Master to Slave when CPOL=1 and CPHA=0.
As can be seen in Figure 12 , CLK is high before data is transferred (idle) (orange box in the figure) , so we can see that POL=1 .
Furthermore, the MOSI data is latched on the falling edge of the first CLK (red line in the figure) , and the MOSI data is changed on the rising edge of the second CLK (green line in the figure) , so we can see that CPHA = 0 .
*The clock polarity has changed, so be careful not to confuse the first and second clock signals.
SPI Mode 3: SPI signal with CPOL=1, CPHA=1
Figure 13: Data transmission waveform from Master to Slave when CPOL=1 and CPHA=1.
As can be seen in Figure 13 , CLK is high before data is transferred (idle) (orange box in the figure) , so we can see that POL=1 .
Furthermore, the MOSI data is changed on the falling edge of the first CLK (green line in the figure) , and the MOSI data is latched on the rising edge of the second CLK (red line in the figure) , so we can see that CPHA = 1 .
To summarize the measurement results from this time, they are as follows (Table 3).
Table 3: Summary of the relationship between the four modes and CPOL and CPHA
| SPI mode | CPOL | CPHA | CLK during idle | First clock | Second CLK |
| mode=0 | 0 | 0 | Low | Data latches at the rising edge. | Change the data on the falling edge. |
| mode=1 | 0 | 1 | Low | Change data at the rising edge. | Latch data at the falling edge. |
| mode=2 | 1 | 0 | High | Latch data at the falling edge. | Data latches at the rising edge. |
| mode=3 | 1 | 1 | High | Change the data on the falling edge. | Data latches at the rising edge. |
6. Conclusion
I actually measured the signals in four different SPI modes, changing CPOL and CPHA. I got confused when the polarity and phase changed while I was taking the measurements myself, but I was able to confirm that it worked as expected. When learning the basics, it might be helpful to not only change the program, build it, and confirm that it works, but also to actually look at the signals to improve your understanding. I encourage you all to try it.
Reference Information
- (Part 1) Basics of SPI communication using NXP's MCX microcontroller and SDK: Actual device testing with two ...
- NXP Interface Products - Summary Page (Japanese Blog)
- Overview of the SPI bus (Japanese blog)
- NXP System Management I²C, I3C, SPI Selector Guide
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In the previous installment, as the first part of our exploration of SPI communication, we used two FRDM boards to run a sample SPI communication application.
This time, we will try changing the settings for four different SPI modes and check the actual SPI signals that are sent and received. This article assumes that you have completed the steps in the following [Part 1] article.
[Part 1] Let's run a sample application for SPI communication.
[Part 2] We will observe the actual SPI signals while changing the SPI mode and see how they change.
(Estimated time: 20 minutes) *Assumes that the content of the first part (MCUXpresso for VSC, SDK installed, and SPI application operation confirmed) has been completed.