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Consult the S32K324 for the simplest write-protection methods

NXP experts:

I have developed a product with S32K324 chip, now I want to burn the program through jlink, I can't read back the burned program through any debugger, if I want to update the program, I can fully erase the flash and then burn it again, is there any such configuration method to prohibit reading the flash? After reading some other posts on the forum, I feel that it is a bit complicated to use HSE to set the password, and I would like to know if there is a simpler way, similar to ST's mcu, to write the configuration bits directly.

Re: 咨询S32K324最简单的写保护方法

Hi @ktwor 

If you prefer not to install the HSE firmware to enable secure debug, there is an alternative option to restrict access to the MCU via JTAG/SWD using a password, without relying on HSE. This approach is discussed in the following thread:

[S32K3] Restrict the debug access with a password when HSE is not used

Please review it and let me know if it meets your requirements.


BR, VaneB

Re: 咨询S32K324最简单的写保护方法

Hi @ktwor 

Please modify the .boot_header as described in Section 32.5.3 of the Reference Manual. Additionally, refer to the image provided in the previously shared link, which also illustrates the required changes.

VaneB_0-1779902701247.pngVaneB_0-1779902701247.png

Re: 咨询S32K324最简单的写保护方法

Hi @VaneB :

    I found that in IVT, there is LF_CONFIG_ADDR. The address of LF_CONFIG_ADDR is 0x007D2000,

ktwor_0-1779888683941.pngktwor_0-1779888683941.png


Re: 咨询S32K324最简单的写保护方法

Hi @ktwor 

Remove only the section corresponding to the XRDC configuration pointer (XRDC_CONFIG_ADDR) and keep all other sections unchanged.

Re: 咨询S32K324最简单的写保护方法

Hi @VaneB :

      I really don't understand how I should modify it. I'm using s32K324. This chip only has CM7_0 and CM7_1, but no CM7_2. So the position of CM7_2 in the IVT is reserved to be larger. Could you help me modify it?

.section ".boot_header","ax"
.long SBAF_BOOT_MARKER /* IVT marker */
.long (CM7_0_ENABLE << CM7_0_ENABLE_SHIFT) | (CM7_1_ENABLE << CM7_1_ENABLE_SHIFT)
.long 0 /* Reserved */
.long CM7_0_VTOR_ADDR /* CM7_0 Start address */
.long 0 /* Reserved */
.long CM7_1_VTOR_ADDR /* CM7_1 Start address */
.long 0 /* Reserved */
.long 0 /* Start Address of Application on CM7_2 Core Reserved*/
.long 0 /* Reserved */
.long LF_CONFIG_ADDR /* Lifecycle configuration pointer */
.long 0 /* Reserved */

Re: 咨询S32K324最简单的写保护方法

Hi @ktwor 

Did you update the IVT? If you refer to section 32.5.3 of the Reference Manual, you will see that after the Start Address of Application on the CM7_2 core, there is a reserved area, followed by the address of the LC configuration word, not the XRDC configuration pointer.

Re: 咨询S32K324最简单的写保护方法

Hi VaneB.

I did a test based on the information you provided, but unfortunately, after I advanced the lifecycle to OEM_PROD and powered off and back on, it was still accessible via SWD without a password, so I don't think my configuration is taking effect!

ktwor_0-1779629094611.pngktwor_0-1779629094611.png

As shown in the figure, I have written the password at 0x1B000080 and 0xDADADADA at 0x7D2000, and changed the LF_CONFIG_ADDR address in startup_cm7.s to 0x7D2000, please give me the possible reasons why the configuration is not working so that I can analyze the issue further, my MCU is S32K324, development environment is s32ds3.4

ktwor_1-1779629192985.pngktwor_1-1779629192985.png


Re: 咨询S32K324最简单的写保护方法

Hi @VaneB :

 I have  Removed only the section corresponding to the XRDC configuration pointer (XRDC_CONFIG_ADDR) and keep all other sections unchanged.However, it still hasn't taken effect and can still be accessed without a password. What else could be the reasons for the configuration not taking effect?

Re: 咨询S32K324最简单的写保护方法

Hi @ktwor 

Just to rule out some possible causes, have you already installed the HSE firmware on your device?

Re: 咨询S32K324最简单的写保护方法

Hi @VaneB :

    HSE has not been installed on my device.I don't have the HSE firmware, so I need to achieve JTAG password access without HSE.

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最后更新:
‎06-05-2026 03:32 AM
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