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LPDDR Design recommendations for S32G Pkg Delay

Hello,

I found this document for the iMX processors:

https://community.nxp.com/pwmxy87654/attachments/pwmxy87654/imx-processors/152878/1/8MN%20HDG%20LPDD...

It does not seem as an official document as I dont see a NXP number on it but it talks about Pkg Delay on Table 2.

In the S32G2HDG Rev. 8, 06/2022 Table 8. S32G LPDDR4 routing constraints, a similar table is provided without Pkg Delay. I was wondering if this parameter is also relevant for the S32G and if so, where can I found the information for it?


Thanks!

Re: LPDDR Design recommendations for S32G Pkg Delay

Hi,

On regards of delay for LPDDR4, the information available under S32G2HDG (the same you are referring to) is the available information. Customer is only required to meet these requirements.

Please, let us know.

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最終更新日:
‎11-21-2025 10:33 PM
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