Hi Leon,
If I'm right this means at the beginning the high side igbt PWM_B(H) = 70% and low side igbt PWM_B(L) = 30% ?
You are correct!
For this I have to get the Gate Signals called "G" but I don't know them.
How could I get them from the duty cycle above ?
You take the PWM duty cycle computed by the SVM (which is between 0 and 1 - you do not need to scale it up to 100% or 1000% since you do not use the hardware) and you transform the value of the duty factor into 2 booleans based on a simple comparison.
I do not know how exactly you are simulation the inverter (powersim or something else) but you need to have the model execution time smaller than the time allocated for PWM computations.
For example: if the FAST LOOP is 100usec (you compute a duty cycle at each 100usec) then if you wish to have a gate command resolution of 1% then you need to simulate the inverter subsystem 100 times faster than the subsystem that computes the duty cycles.
e.g. if you wish to have 70% ON for IGBT A(H) then you keep G A(H) ON for 70 cycles and then you switch it OFF and do the opposite for the lower part.
In theory - the inverter and motor shall be simulated with the smallest step possible in order to replicate the continuous time domain. In this case you need to have the inverter and motor simulated @ 1e-6seconds (might be over-killing for a PC)
Hope this helps!
Daniel