S32DS Component about MPC5746C eMIOS IPWM Mode

[shijie_zheng]

I use S32DS to config eMIOS IPWM Mode in MPC5746C,I have the following questions。

TypeH Channel 11  are used to collect the pulse of the input waveform,eMIOS1 CLK is set to 80MHZ.

I also config eMIOS_Mc1 as follows:

Question 1:I don't understand the meaning of Clock Divide, how many should we set?

Question 2:I want use MC Counter up mode,choose eMIOS counter bus A,but I  don't really understand how Period is set up, The input waveform I need to measure is as follows,I want to know the relation between the input waveform and Period。

Type H Channel 11 config as follows:

Can anyone answer the above question? Thank you。

[PetrS]

Hi,

the eMIOS module has a global prescaler, it divides eMIOS module clock which is then source clock for each channel. The channel itself has an internal divider, which divides that global clock. So in your case the channel 23 counter is clocked with 80MHz/(79+1)/1 = 1MHz, period is 1us. This determines measurement resolution.

The ch23 counter counts to your predefined 5000, that represents 5ms. As the input channel is using this Counter bus A, it is not ideal for your input signal, you should have longer period so you do not need to care about overflow so often.

If you need not to set counter bus period just set max value (0xFFFF).

BR, Petr

[shijie_zheng]

Thanks petr for response，your answer is very useful.
I understand the relation of clock divide you mentioned，

I have made the following Settings in the eMIOS MC configuration:
1.Enable Global Prescaler
2.Set clock divide to 79 (1MHZ)
3.Enbale Global Timebase
4.Disbale External Timebase
I want use Type H Channel 11 as input channel,

For example,The input waveform Cycle I want to measure is 30ms.
and i use Global counter bus A(channel 23) as input channel time base.
so the Period value for MC should be set 30000 (1us*30000=30ms)
Do I understand it correctly?

If i want to avoid overflow, Do I have to set Period to be more than 30000(for example 30001 or more)?

[PetrS]

Hi,

you will always have a overflow, it depends how often. If the period of used counter bus is less then period of input signal, the overflow happens for each input signal period (can be multiple time based on ratio). If the counter bus period is much longer then period of input signal, then overflow happens in much lower rate.

BR, Petr