MPC5777c - eTPU resolver ATO setting

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MPC5777c - eTPU resolver ATO setting

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hanryang
Contributor II

Hello.

I got some question for MPC5777c and eTPU resolver.

 

1. SDADC

I want to get Resolver's SIN and COS signal through this process : SDADC -> eDMA -> eTPU.

 

There are SDADC_0, SDADC_1, SDADC_2, SDADC_3 eDMA_B channel request allocation on MPC5777c Reference Manual .

hanryang_3-1729728631181.png

There are SDADC_1, SDADC_2, SDADC_3, SDADC_4 trigger inputs on MPC5777c Reference Manual .

hanryang_1-1729728617744.png

hanryang_5-1729729787536.png

Source Code doesn't have SDADC_0.

 

Q1. 

Why are the numbers of SDADC modules different when used as "SDADC trigger inputs" and when used in "eDMA_B channel request allocation"?

 

Q2.

In this case, SDADC -> eDMA -> eTPU Which SDADC_x, SDADC_y should I use to get the SIN and COS signals of the resolver through this process?

 

 

2.eTPU resolver ATO Channel Setting

I'm trying to apply eTPU Resolver for my SW.

The code in the figure below is included in etpuRDCCUG.pdf.

hanryang_4-1729728804693.png

ETPU_RESOLVER_ATO_CHAN /* chan_num_dma - etpuA1 generate dma request on channel DMA_A 28 */

 

Q3.

Does this code mean that I need to use dma to access etpu to use ATO?

 

Thanks for always helping me.

Have a great day.

 

 

 

 

 

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davidtosenovjan
NXP TechSupport
NXP TechSupport

The table is wrong, following is correct (reserved values should be at the end, not in the middle):

davidtosenovjan_0-1729855606264.png

SDADC modules are supposed to be marked as SDADC_1 to SDADC_4 (not 0-3). So in the table 4-6 it is incorrect (I have never noticed to be honest).

Here I shared example code in the past:

https://community.nxp.com/t5/MPC5xxx-Knowledge-Base/Example-MPC5777C-SDADC-eTPU-triggered-GHS714/ta-...

However please be aware that once enabled the SDADC keeps running. There is no “Single conversion mode”. This requires that the CDATA register be continually drained by DMA or ISR.
eTPU triggering is only related to synchronous start of these modules, nothing else.

From SDADC to eTPU there may be signal about valid data available or conversion watchdog limit and opposite way, eTPU may gate interrupt or DMA transfers.

davidtosenovjan_2-1729856138005.png

 

 

 

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davidtosenovjan
NXP TechSupport
NXP TechSupport

The table is wrong, following is correct (reserved values should be at the end, not in the middle):

davidtosenovjan_0-1729855606264.png

SDADC modules are supposed to be marked as SDADC_1 to SDADC_4 (not 0-3). So in the table 4-6 it is incorrect (I have never noticed to be honest).

Here I shared example code in the past:

https://community.nxp.com/t5/MPC5xxx-Knowledge-Base/Example-MPC5777C-SDADC-eTPU-triggered-GHS714/ta-...

However please be aware that once enabled the SDADC keeps running. There is no “Single conversion mode”. This requires that the CDATA register be continually drained by DMA or ISR.
eTPU triggering is only related to synchronous start of these modules, nothing else.

From SDADC to eTPU there may be signal about valid data available or conversion watchdog limit and opposite way, eTPU may gate interrupt or DMA transfers.

davidtosenovjan_2-1729856138005.png

 

 

 

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