MPC5775B Linker section failure while adding a new component into an example code

[DivyaVyas]

Hello,

Context:
I am working with ENET and PHY modules and testing ping response on the MPC5775B microcontroller.
Initially, the project was functioning correctly. However, when adding a UART component, a linker section overlap issue occurred.
The project uses  linker_flash.ld file.

Issue: 

Please find the error details in the error.txt file kept in below link.

https://github.com/Divya-stack-eng/MPC5775B_LinkerAndMapFiles.git

Observation on checking the map file:

The following sections are overlapping in their Load Addresses (Flash memory):

1. .NULLoverlaps with.sdata (0x00815100 vs 0x008150f4).
2. .sbss overlaps with .code (0x00815104 starts both).
3. .iplt overlaps with stack (0x008152c0 starts both).

Please find the linker file and map file, attached herewith. 

https://github.com/Divya-stack-eng/MPC5775B_LinkerAndMapFiles.git

Please provide suggestions to resolve this.

Thanks alot in advance,

Best Regards,

Divya 

[davidtosenovjan]

Unfortunately your links are not visible to me.

Usually it is possible to modify linker command file address ranges to fit the need of your code. Lengthen some segments and shorten others.

[DivyaVyas]

Hello,

Error: "section .NULL LMA [00815100,00816f27] overlaps section .sdata LMA [008150f4,00815103]
collect2.exe: error: ld returned 1 exit status"

For resolving the overlap error, I increased the alignment for .sdata section from 4 to 16. 

Also, I added a buffer space of 0x300 in .sdata to prevent overlap. 

I made .NULL defined explicitly in linker script, ensuring that it starts after .sdata_end_..

Then, I could find the error being resolved. But, upon flashing, I could find IVOR13 (Data TLB Error Interrupt, which was triggering SWTI IRQ Handler. 

For checking it better, I created a new project. Added Enet and Phy components.

There was no overlap error. But, I could find IVOR1 exception (Machine check) while flashing. 

Upon enabling the FEC internal clock (FEC0_Clk), the error got resolved. But still upon executing Phy_Init, IVOR14 is encountered. I understand that the MDIO interface has to be enabled and ENET peripheral has to be made to run mode, before Phy_init. Probably this can be the root cause.  In MPC5775B reference manual, I couldn't find MC_ME or clock generation module. Would you suggest how to enable Enet and MDIO. How to ensure that ENET is in RUN mode before PHY initialization, in MPC5775B.

int main(void)
{
  /* Write your local variable definition here */

  /*** Processor Expert internal initialization. DON'T REMOVE THIS CODE!!! ***/
  #ifdef PEX_RTOS_INIT
    PEX_RTOS_INIT();                   /* Initialization of the selected RTOS. Macro is defined by the RTOS component. */
  #endif
  /*** End of Processor Expert internal initialization.                    ***/

	/* Initialize clocks */
	CLOCK_SYS_Init(g_clockManConfigsArr, CLOCK_MANAGER_CONFIG_CNT, g_clockManCallbacksArr, CLOCK_MANAGER_CALLBACK_CNT);
	CLOCK_SYS_UpdateConfiguration(0U, CLOCK_MANAGER_POLICY_AGREEMENT);

	/* Initialize pin configurations */
	PINS_DRV_Init(NUM_OF_CONFIGURED_PINS, g_pin_mux_InitConfigArr);

	/* Configures the SIU (System Integration Unit) */
	SIU->FECCR &= ~SIU_FECCR_FM_MASK; // Specifically, it clears the FM (Fault Mode) bit in FECCR (Fault Error Control Register)

	/* Initialize Ethernet */
	ENET_DRV_Init(INST_ETHERNET1, &ethernet1_State, &ethernet1_InitConfig0, ethernet1_buffConfigArr0, ethernet1_MacAddr);

	/* Initialize PHY */
    PHY_Init(phy);

	/* Main loop */
	for (;;) {
		/* Insert a small delay to make the blinking visible */
		delay(720000);
		/* Toggle output value LED2 */
		PINS_DRV_TogglePins(LED1_PORT, (1 << LED1_PIN));
	}

  /*** Don't write any code pass this line, or it will be deleted during code generation. ***/
  /*** RTOS startup code. Macro PEX_RTOS_START is defined by the RTOS component. DON'T MODIFY THIS CODE!!! ***/
  #ifdef PEX_RTOS_START
    PEX_RTOS_START();                  /* Startup of the selected RTOS. Macro is defined by the RTOS component. */
  #endif
  /*** End of RTOS startup code.  ***/
  /*** Processor Expert end of main routine. DON'T MODIFY THIS CODE!!! ***/
  for(;;) {
    if(exit_code != 0) {
      break;
    }
  }
  return exit_code;
  /*** Processor Expert end of main routine. DON'T WRITE CODE BELOW!!! ***/
} /*** End of main routine. DO NOT MODIFY THIS TEXT!!! ***/

Thank you so much,

Divya V

[DivyaVyas · Accepted solution]

Hello,

I could resolve the IVOR14 exception. All exception issues and memory issues are resolved.

Following sequence is required for the current PHY:

* Step 1: Initialize ENET (Ethernet MAC) */
ENET_DRV_Init(INST_ETHERNET1, &ethernet1_State, &ethernet1_InitConfig0,
ethernet1_buffConfigArr0, ethernet1_MacAddr);

/* Step 2: Enable MDIO (Management Data Input/Output) */
ENET_DRV_EnableMDIO(INST_ETHERNET1, false); // false = Do not disable preamble

/* Step 3: Initialize PHY Framework */
PHY_FrameworkInit(&phyConfig[phy], &phyDrivers[phy]); //to initialize the config pointers

/* Step 4: Initialize PHY (Registers, Basic Setup) */
PHY_Init(phy);

/* Step 5: Enable Auto-Negotiation */
PHY_EnableAutoneg(phy);

/* Step 6: Enable PHY Interrupts */
PHY_EnableInterrupts(phy);

/* Step 7: Verify PHY Link Status */
PHY_GetLinkStatus(phy, &linkstateUp);
if (!linkstateUp)
{
// Handle No Link Error
}

These changes are needed since the current PHY we are using is KSZ8061RNB, and we have configured the PHY type as Generic.
Also, Since 2 pairs of wires are used, Auto negotiation is opted in HW (via pin strapping) and SW Configurations. 

Thanks, and Kind Regards,
Divya V