MPC5748G Flash example code question DisableFlashControllerCache function

[MattJCole]

I have read through the data sheet for the processor, and I am still do not know what sections in flash the P0_BFEN, P1_BFEN, P2_BFEN control. I know I need to clear the bit before I write to flash and restore the bit after I am done writing to flash. Below are the flash addresses I will be writing to. What flash addresses does P0_BFEN, P1_BFEN, and P2_BFEN control

1. 0x00FD8000 - 0x00FD8018
2. 0x00FE0000 - 0x00FE0018
3. 0x00FF0000 - 0x00FFFFFF
4. 0x01000000 - 0x012BFFFF
5. 0x012C0000 - 0x0157FFFF

[lukaszadrapa · Accepted solution]

Hi,

In the past, I got confirmation that it is not necessary to explicitly clear the read line buffers:

“the flash controller samples the prog/erase status sidebands and uses these to automatically clear the read line buffers whenever a program or erase are in progress.”

And there’s this note in reference manuals for the MPC57xx devices which confirms it:

“To clear the flash controller line read buffers, issue an interlock
write command to a valid flash memory address. There will not
be an actual flash program operation performed, but the flash
controller mini-cache will be cleared as a side effect of
executing the command.”

That means the interlock write issued during program/erase operation clears the buffer.

So, it’s safe to remove the functions which disable/restore the buffer.

And to answer your question – you are not configuring PFCRn registers for certain addresses, you are configuring PFCRn registers for bus masters. This table should explain it:

Regards,
Lukas

[MattJCole]

That makes sense. Thought you where controlling the sections of flash you are actually contorting the bus from the processor to flash. One last question. How do you perform an interlock write?  

[lukaszadrapa]

That's a part of program and erase sequence:

And here is a description how to perform dummy interlock write: