Hi Rhea,
Do you mean that 1uF capacitor is the only one at VDD_LV? The specification says that minumum capacitance is 4.7uF:

And it’s minimal value. It should be validated by user for given application.
It is also recommended to use Progressive Clock Switching feature to avoid current spikes. Search for „Progressive Clock Switching“ in the reference manual for details.
Regards,
Lukas