MPC5674F into slow mode

[vincentbbbb]

Hello,

I was wondering how it was possible to put the MPC5674F into `slow mode` like mentioned in the documentation:

1.2.2 Low-Power Modes
The MPC5674F includes two special modes to allow reduction of application power consumption:
• Stop mode: System clock stopped to all modules including the CPU. Wake-up timer used to restart
the system clock after a predetermined time.
• Slow mode: Allows the device to be run at very low speed (approximately 1 MHz), with modules
(including the PLL) selectively disabled in software.

Regards,

[davidtosenovjan]

I don't think such dedicated special mode would be there. It only mentions it is possible to configure clock to run down 1MHz, what's not common standard, but there is no dedicated 'slow' low power mode.

[vincentbbbb]

Thank,,

But I was wondering what are the PLL config to put it at 1MHz.  Is it by using external clock???

[davidtosenovjan]

Either external or you use SYSCLKDIV divider. For instance you can setup PLL for 16MHz output (considering 16MHz crystal) and SYSCLKDIV for value of 16 => 1MHz system clock.

[vincentbbbb]

Thanks for the info,

Do you know if this setting is used when we are using the JTAG.  I am connecting through the JTAG to access memory (without init from the CPU)..  How is the frequency computed then??

[davidtosenovjan]

The recommended maximum JTAG frequency is 1/4th of the core frequency. (In this case 250kHz)

[vincentbbbb]

I understand the JTAG frequency is 1/4th of the core frequency, but the SIU_SYSCLKDIV is a register set at runtime or set once and will maintain its value after reset??

Regards  

[davidtosenovjan]

JTAG frequency is being set on the side of debugger, for instance here (considering TRACE32 debugger):

So it you change frequency significantly wanting to keep debugging during this "slow mode", you change this clock to keep 1/4th of the core frequency or you can have set for such slow clock for the whole time.