MPC5644A - SWT - Software WatchDog Timer

[ShadowShooTR]

Hi all,

I've two questions about SWT settings.

First of all, In referance manual  there is a softlock bit  which makes the regs are writeable and readable or just readable.  I've wanted to try it as shown below.

ShadowShooTR_1-1613116846857.pngShadowShooTR_2-1613117113424.png

It works fine like this. However, when the MCR is locked state , I've tried to reach that register (MCR) without removing the lock. It immediately causes the system reset.

Then I realize that there is  RIA bit in MCR register. When I read its definition, I understand that when a invalid access happens, the SWT generates just error not system reset (IF MCR_RIA = 0 ).

ShadowShooTR_0-1613116701300.png

I've changed RIA as 0, and tried again, but it still resets.

Is there a something that I missed ?  

The second question is :

I wanted to lock those registers especially MCR so that it is not accessible even if it's almost unlikely. Because there is MAPn bits which make the master accesses enable/disable. I've seached its meaning in MPC5644A r.m but didn't found.  I've found in 5674F r.m 

ShadowShooTR_4-1613118189159.pngShadowShooTR_3-1613118144239.png

I've disabled the core 0 access by setting MCR_MAP0 = 0 then the whole system is crashed .

Could you explain that why there is a selection like this ? How can I use MCU when I  disable the CPU instruction access. Maybe , it is designed as if several core existence but there is one core . 

Thank you in advance.

Regards.

 HG 

[davidtosenovjan · Accepted solution]

Regarding second question - The description you may find on the first page of XBAR chapter:

davidtosenovjan_0-1613145495590.png

It you speak about SWT_MCR[MAPx] fields, then it only affects accesses to SWT. Theoretically it can be handled by DMA for instance, although it does not make to much sense. But mainly, it'll be generic module for multiple devices. Yes, it can be used with devices where masters are mapped differently.

[ShadowShooTR]

Thank you for your help.

[davidtosenovjan]

Hi,

in the SIU_DIRER register is also option to choose whether IVOR0 or IVOR1 is supposed to be generated and this needs to be unmasked by settting MCR[CE] or MSR[ME].

davidtosenovjan_0-1613128624432.png

[ShadowShooTR]

Hi @davidtosenovjan 

I see, you mean an invalid acces to SWT will always cause an interrupt. If SWT bus error occurs, interrupt can be selected as you said.

So, it can be handled in IVOR0 or IVOR1 traps am I right ? 

[davidtosenovjan]

It goes into IVOR1 (i.e. bus error) as service sequence is invalid what implies watchdog is not serviced and device is reset by SWT itself subsequently.

[ShadowShooTR]

Well, it's understood. Thank you Mr @davidtosenovjan .

Do you any thoughts/comments about my second question ?