We have an external watchdog for our MPC5121e processor that resides inside an FPGA. The FPGA has connections to both the HRESET and SRESET lines.
Currently, when the watchdog trips, the FPGA pulls both the HRESET and SRESET lines low simultaneously and releases them 10ms later.
In some rare instances, the MPC5121e does not act as if has processed the reset.
Is there any problem with pulling both the HRESET and SRESET lines down at the same time? If these lines were slightly skewed because of some slight delay differences could that explain this result?