IVOR 13 TLB Error

[elifceliker]

Hi,

I used to below code for generating 2-bit ECC error in RAM however generate1bitECCError() runs correctly but generateNoncorrectableECC_error () returns IVOR13 TLB error. I also tried to What is reason behind Data TLB error(IVOR13)? plea... - NXP Community but I didnt  check the MMU table because I didnt find it where it is.Any help will be appreciate,thanks a lot.

[lukaszadrapa]

Hi Elif,

did you use GHS Multi IDE or did you ported the code to S32DS? Most likely, there's a problem with your exception handler. Please check if IVPR+IVOR1 registers (base address + offset) really points to your machine check handler.

Regards,

Lukas

[elifceliker · Accepted solution]

Hi Lukas,

I ported the code to S32DS .I checked the registers which you told me but when optimization is OFF, IVOR1_Exception_Handler function could not return to epilog_IVOR1. At the first instruction of IVOR1_Exception_Handler, we saw that lr showing the address of epilog_IVOR1.
At the last instruction of IVOR1_Exception_Handler, we saw that lr showing the wrong address.

-c -fmessage-length=0 -fstrict-volatile-bitfields -mlra -msdata=eabi

//// main.c
static void generateNoncorrectableECC_error(void)
{
volatile uint32_t test_read = 0;

/* invert 2 LSB bits to create non-correctable data error */
EIM->EICHDn[0].WORD1 = 0x00000003;
/* PRAMC_0 channel error injection enable */
EIM->EICHEN = 0x80000000;
/* global error injection enable */
EIM->EIMCR = 1;

/* error caused by read (it should set MCSR[MAV, LD, BUS_DRERR]) */
//test_read = test[0];
test_read = test[0];
}
////////

////// exception.c
void foo()
{
int x = 0;
}

void IVOR1_Exception_Handler(void){

foo();
}

IVOR1_Handler:
prolog_IVOR1:
e_stwu r1, -0x50(r1) # Create stack frame and store back chain
se_stw r0, 0x10(r1) # Store GPR0 (working register)
se_mflr r0
se_stw r0, 0x14(r1) # Store LR
se_mfctr r0
se_stw r0, 0x18(r1) # Store CTR
mfxer r0
se_stw r0, 0x1C(r1) # Store XER
mfcr r0
se_stw r0, 0x20(r1) # Store CR
e_bl prolog_GPRs # Store GPR3-GPR12 (stack offset 0x24-0x48)

mfmsr r0 # As function prologs/epilogs may contain
e_or2is r0, 0x0200 # SPE instruction, enable SPE, as MSR
mtmsr r0 # register is cleared at this point

e_bl IVOR1_Exception_Handler # Invoke exception handler

epilog_IVOR1:
e_bl epilog_GPRs # Restore GPR3-GPR12 (stack offset 0x24-0x48)
se_lwz r0, 0x20(r1)
mtcr r0 # Restore CR
se_lwz r0, 0x1c(r1)
mtxer r0 # Restore XER
se_lwz r0, 0x18(r1)
se_mtctr r0 # Restore CTR
se_lwz r0, 0x14(r1)
se_mtlr r0 # Restore LR
se_lwz r0, 0x10(r1) # Restore GPR0 (working register)
e_add16i r1, r1, 0x50 # Clean up stack
se_rfmci
;# End IVOR1 Exception Handler

I used to above code,any help will be appreciate,thanks a lot.

Elif

[elifceliker]

Hi Lukas,

I ported the code to S32DS .I checked the registers which you told me but when optimization is OFF, IVOR1_Exception_Handler function could not return to epilog_IVOR1. At the first instruction of IVOR1_Exception_Handler, we saw that lr showing the address of epilog_IVOR1.
At the last instruction of IVOR1_Exception_Handler, we saw that lr showing the wrong address.