How to get the last valid instruction address if IVOR3 exception interrupt is triggered (MPC5748G)

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How to get the last valid instruction address if IVOR3 exception interrupt is triggered (MPC5748G)

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FAISAL0323
Contributor II

Hi Experts

I encountered a problem in my application program in which the exception interrupt IVOR3 is triggered due to a wrong stack operation probably. Through debugging it is found that contents of SRR0, SRR1 and LR register are as follows.(Images are also attached for convenience). 

SRR0= 0x00000000

SRR1= 0x00000000

LR = 0x00000000

FAISAL0323_0-1654744855363.png

FAISAL0323_1-1654744895682.png

 

Since there is nothing in SRR0, SRR1  and LR register, Please let me know, how I can  get the last valid instruction address keeping in mind IVOR3 is triggered. 

Thank you very much!

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davidtosenovjan
NXP TechSupport
NXP TechSupport

It is interesting. Have you looked directly to SPR register? Is this error injected or you are facing some issue?

SRR0 should contain the fault address, it is correct. If there is 0 on that place then it is either not updated (IVOR didn't happen and you are in IVOR3 ESR due to different reason, for instance SW error) or reported address is 0, what's quite improbable.

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FAISAL0323
Contributor II

Thanks David for your reply.

It was issue which we were facing in which IVOR was triggered. you mention about SW error. Would you please explain bit more what is SW error?

 

As far as reasons for reported address 0 is concern, We have found that , LR register is created on the top zone of SafeRTOS task stack, and the content of LR is 0x00000000. If "Return()"is used in our task and executed unfortunately, the pc point will go to LR and IVOR3 exception interrupt will be triggerd with LR,SRR0 and SRR1 with bogus address 0. 

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davidtosenovjan
NXP TechSupport
NXP TechSupport

If it is so, then it could be correct MCU reaction when jumping to address 0. Please consult with RTOS support as it seems to be SW issue.

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