Hi, the portion of SRAM you want to test is needed to set for cache inhibited attribute i.e. to set up particular TLB entry in the MMU table. You may use following utility for simplifying of TLB configuration:
MMU Assist Register CONFIGURATOR
Note that every debugger or most of debuggers will be able to show MMU table in the screen like this:

Also I would like to point out following presentation, page 89-107:
e200 Core Training relevant to MPC55xx and MPC56xx device family
Note that if you have already stored some data and you are using copy-back mode, it may be necessary to invalidate the flash content.
You could also see following example code, file Optimizations.c, you may see there how to invalidate cache and also how to MMU attribute from cacheable to cache inhibited (but I must note it has been written for different device, so it may be slightly different):
Example XPC567XFKIT PinToggleStationery CW210