DMA Issue in MPC57xx

[meedandeys]

Hello Folks,

I am working on the DMA driver for MPC5744P. I am facing below issue, any direction/thoughts on this would be of great help.

I have set up my DMA TCDs to transfer data in RAM from Buffer1 to Buffer2. When I initiate DMA transfer, I observe DMA engine stops after 1 iteration of major loop . There were no errors reported in the DMA Error Status register. Below are my TCD configurations.

Note: when when i change my Minor loop to n bytes and Major loop = 1, then DMA works fine.

For some reason my Major loop does not run for more than 1 iteration. Any thoughts on this would be of great help

Below is code which i am trying out

#define BUFFER_LEN 12

const unsigned char Buffer1[BUFFER_LEN] = "Hello World"

unsigned char Buffer2[BUFFER_LEN];

void edma_config()

{  

  DMA_0.TCD[1].SADDR.R = (unsigned long)&Buffer1;               /* Load address of source data and adjust for size */

  DMA_0.TCD[1].ATTR.B.SSIZE = 0;                                /* Read 2**0 = 1 byte per transfer */

  DMA_0.TCD[1].ATTR.B.SMOD = 0;                                 /* Source modulo feature not used  */

  DMA_0.TCD[1].SOFF.R = 1;                                      /* After transfer, add 0 to src addr */

  DMA_0.TCD[1].SLAST.R = 0;                                     /* After major loop, adjust the source address  */

  DMA_0.TCD[1].DADDR.R = (unsigned long)&Buffer2;

  DMA_0.TCD[1].ATTR.B.DSIZE = 0;                                /* Write 2**0 = 1 byte per transfer  */

  DMA_0.TCD[1].ATTR.B.DMOD = 0;                                 /* Destination modulo feature not used  */

  DMA_0.TCD[1].DOFF.R = 1;                                      /* Increment destination addr by 1 */

  /* If you are executing more than one time, you need to subtract NUMBER_OF_BYTES here instead of 0 */

  DMA_0.TCD[1].DLASTSGA.R = 0;                                  /* After major loop, adjust the destination address */

  /* If you want to keep going, set this to 0 to keep the channel enabled */

  DMA_0.TCD[1].CSR.B.DREQ = 1;                                  /* Disable channel when major loop is done*/

  DMA_0.TCD[1].NBYTES.MLNO.R = 1;                               /* NBYTES - Transfer 1 byte per minor loop */

  DMA_0.TCD[1].CITER.ELINKNO.B.CITER = BUFFER_LEN;              /* Init. current interaction count */

  DMA_0.TCD[1].BITER.ELINKNO.B.BITER = BUFFER_LEN;              /* Minor loop iterations */

  /* RM reccomendations end here */

  DMA_0.TCD[1].CITER.ELINKNO.B.ELINK = 0;                       /* No Enabling channel LINKing */

  DMA_0.TCD[1].BITER.ELINKNO.B.ELINK = 0;                       /* No Enabling channel LINKing */

  DMA_0.TCD[1].CSR.B.MAJORELINK = 0;                            /* Dynamic program is not used */

  DMA_0.TCD[1].CSR.B.ESG = 0;                                   /* Scatter Gather not Enabled */

  DMA_0.TCD[1].CSR.B.BWC = 0;                                   /* Default bandwidth control- no stalls */

  DMA_0.TCD[1].CSR.B.INTHALF = 0;                               /* No interrupt when major count half complete */

  DMA_0.TCD[1].CSR.B.INTMAJOR = 0;                              /* No interrupt when major count completes */

  DMA_0.TCD[1].CSR.B.MAJORLINKCH = 0;                           /* No link channel # used */

  DMA_0.TCD[1].CSR.B.DONE = 0;

  DMA_0.TCD[1].CSR.B.ACTIVE = 0;

  DMA_0.TCD[1].CSR.B.START = 1;                                 /* Initialize status flags START, DONE, ACTIVE */

}

[meedandeys]

Hello Peter,

Thank you for the example code. I checked your example and find that your are setting the Major loop count to 1. Did you try setting the Major loop count to more than 1 ?

Major count of 1 has no issue in my configuration. When i change my Major count to more than 1 then the problem starts.

Also I saw your PLL0 is set to 200Mhz (system clock) and PBRIDGE is set to 50Mhz.

I had trouble configuring DMA (DMA address space not visible) with PLL0 = 90Mhz and PBRIDGE = 30Mhz. Did you try with these configuration ?

The MPC5744P part which i have supports only 180MHz frequency, so i cannot use your PLL0/PBRIDGE settings.

[petervlna]

For each major loop iteration you need to set START bit (by SW or by HW trigger).

For block of data transfer you will use minor loops.

For example: HW trigger

When ADC data measurement is done (ADC result registers are filled with valid data), ADC request DMA to transfer all data from result registers to RAM buffer. In case you need to maintain last 3 measurements you will use major loops with offset.

Each major loop will be triggered from Valid ADC data flag. After 3 major loop iterations major loop counter resets.

Example: SW trigger

In ADC end of conversion interrupt you will write to START bit by SW to start DMA transfer.

Peter

[meedandeys]

Peter,

Thank you for the explanation. My goal is to implement/migrate DMA based UART Tx/Rx from MPC5643L to MPC5744P. 

The MPC5744P part which i have supports only 180MHz frequency,

When i am trying to configure PLL0 at 180 Mhz (system clock) and PBRIDGE at 30Mhz, I had trouble configuring DMA (DMA address space not readable/writable) Any thoughts on this ? I tried contacting our NXP focal, he too observed this issue.

The clock frequencies (DMA = 90Mhz and DMA_MUX = 30Mhz) didnt work for me hence now i am operating at PLL0 at 180 Mhz and PBRIDGE at 45Mhz.

I went through several examples in forum, all are based for Linflex_0, do you have any examples for Linflex_1 module ? Technically it should be identical for both channels. I observed Linflex_0/1 Tx/RX are on DMA_MUX_0 & 1 channels, hence i might be missing some configuration ?

For some reason my DMA module is not getting the correct Major loop triggers from DMA_MUX. Any debugging tips on this would help ?

[petervlna]

Hi,

I suggest you to check the examples for MPC57xx DMA here on community:

Example-MPC5744P-DMA-v1_0-GHS614.ZIP

There is really no issue with DMA if you configure it properly.

Do not forget to grant DMA access to requested Slaves in AIPS bridge!

Peter

[meedandeys]

Also i have provided access DMA access to slaves on APIS bridge and DMA is set to highest priority on the XBAR switch