******************************************************************************** * Detailed Description: * * Application performs basic initialization, setup PLLs. * DSPI_A is configured as master using DMA to send/receive 8 words. * * Two DMA descriptors are initialized: * - TCD[32] master transmit * - TCD[33] master receive * * * EVB connection: * * Do external loopback to connect SOUT to SIN * * PM6 ... SCKA * PM7 ... SINA * PM8 ... SOUTA * PM13... PCSA0 ** * ------------------------------------------------------------------------------ * Test HW: MPC5777C-512DS Rev.A + MPC57xx MOTHER BOARD Rev.C * MCU: PPC5777CMM03 3N45H * Fsys: PLL1 = core_clk = 260MHz, PLL0 = 200MHz * Debugger: Lauterbach Trace32 * Target: internal_FLASH * *********************************************************************************

Hi,    Please update your Cyclone Flash Programming Algorithms for MPC57xx through the link.      http://www.pemicro.com/support/flash_list_menu.cfm     Older code algorithms includes area of HSM. If there are ECC errors in these blocks, the device may stuck in reset. During reset, the SSCM module searches for valid boot header. If it reads corrupted data from HSM blocks, it will not exit the reset.     Newer should be with “NO_BASE_ADDRESS=00F90000/”   https://community.nxp.com/thread/444748   Failed sample waves on PORST vs RESET are as below.    Algorithms in S32DS_Power_v2_1 and S32DS_Power_v2017_R1 are good.     Regards Oliver

******************************************************************************** * Detailed Description: * * Example shows how to trigger ADC conversion on falling edge of PWM signal. * eMIOS ch1 is set to SAIC mode and a flag generated on selected edge detection * triggers BCTU channel which starts conversion of ADC1 ch9. On this channel * the board's trimmer is connected. * * EVB connection: * * J3.1 .. PA[1] - connect external PWM signal * J3.3 .. PA[2] - toggled in BCTU interrupt after ADC measurement * * ------------------------------------------------------------------------------ * Test HW: DEVKIT-MPC5748G * Maskset: 0N78S * Target : FLASH * Fsys: 160 MHz PLL * Debugger: Lauterbach * ******************************************************************************** Revision History: 1.0 Nov-5-2019 Petr Stancik Initial Version *******************************************************************************/

******************************************************************************** * Detailed Description: * * eMIOS0 ch0 is set to SAIC mode generating interrupt on falling edge. * The IGF ch16, connected to eMIOSch0, is set to filter low pulses <1.5us * Intergation filter type is used for falling edge with given threshold. * eMIOS interrupt is called if input signal low pulse is longer than 1.5us. * * ------------------------------------------------------------------------------ * Test HW: MPC5777C-512DS Rev.A + MPC57xx MOTHER BOARD Rev.C * MCU: PPC5777CMM03 2N45H CTZZS1521A * Fsys: PLL1 = core_clk = 264MHz, PLL0 = 192MHz * Debugger: Lauterbach Trace32 * Target: internal_FLASH * Terminal: 19200-8-no parity-1 stop bit-no flow control on eSCI_A * use USB connector (J21) on minimodule * * EVB connection: ETPUA30 (PortP P23-15) --> USER_LED_1 (P7-1) * ETPUA31 (PortP P23-14) --> USER_LED_2 (P7-2) * * eMIOS ch0 (PortG P14-16)--> connect external pulse signal * ********************************************************************************

******************************************************************************** * Detailed Description: * Application performs basic initialization, setup PLL to maximum allowed * frequency * * User can choose, which low power mode should be entered. There is LPU_MODE * macro defined, which allows to choose STOP, STANDBY or LPU_RUN mode. * * If LPU_RUN mode is selected, user can use macro LPU_STOP_SLEEP_STANDBY, * which allows to choose LPU_STOP, LPU_SLEEP or LPU_STANDBY mode. * * Ther is also RTC initialized, which wakeup microcontroller using WKPU after * 5 seconds from some of the LPU is entered. RTC uses FIRC as a source clock, * so FIRC must be enabled in all low power modes. * * * Modified files: mem.ld, sections.ld, startup.s, added file z2_restart.s * * * ------------------------------------------------------------------------------ * Test HW:         MPC5748G-324DS, MPC574xG Motherboard * MCU:             PPC5748GMMN6A 0N78S * Fsys:            PLL0 160MHz * Debugger:        Lauterbach Trace32 *                  PeMicro USB-ML-PPCNEXUS * Target:          internal_FLASH (debug mode, release mode) * EVB connection:  USER LED1 to A1 *                    USER LED2 to A2 * * * ********************************************************************************

******************************************************************************** * Detailed Description: * A simple example configures eTPU engine B channels 0/1 for QOM and FPM. * Connect these pins by wire. Output wave is generated on chnl ETPUB0 (QOM0) * and its frequency is measured on the chnl ETPUB1 (FPM0). * TCR counter frequency is 64MHz, output wave configured as 1MHz ( expected * frequency measured by FPM. Window size is 28us (0x400) thus number of * measured pulses is 28 (27 initally). * * Note: It is needed to configure IGF module, otherwise inputs does not pass * to eTPU module. * * ------------------------------------------------------------------------------ * Test HW:         MPC5777C-512DS Rev.A + MPC57xx MOTHER BOARD Rev.C * MCU:             PPC5777CMM03 2N45H CTZZS1521A * Fsys:            PLL1 = core_clk = 264MHz, PLL0 = 192MHz * Debugger:        Lauterbach Trace32 * Target:          internal_FLASH * EVB connection:  ETPUB0 (PortR P25-1) --> ETPUB1 (PortR P25-0) by wire * ********************************************************************************

******************************************************************************** * Detailed Description: * Application performs basic initialization, initializes interrupts and NMI for * WKPCFG pin (GPIO213). * User needs to connect ETPUC9 pin to user switch and general purpose output * ETPUA30 to user LED 1: * ETPUA30 (PortP P23-15) --> USER_LED_1 (P7-1) * WKPCFG  (PortC P10-4)  --> USER_SWITCHES (P6-4) * Jumper J523 position 1-2 needs to be OPEN! * * If rising edge is detected (i.e. button is pressed), machine check exception * is triggered and LED1 on is toggled. * * ------------------------------------------------------------------------------ * Test HW:         MPC5777C-512DS Rev.A + MPC57xx MOTHER BOARD Rev.C * MCU:             PPC5777CMM03 2N45H CTZZS1521A * Fsys:            PLL1 = core_clk = 264MHz, PLL0 = 192MHz * Debugger:        Lauterbach Trace32 * Target:          internal_FLASH * Terminal:        19200-8-no parity-1 stop bit-no flow control on eSCI_A * EVB connection:  ETPUA30 (PortP P23-15) --> USER_LED_1 (P7-1) *                  WKPCFG  (PortC P10-4)  --> USER_SWITCHES (P6-4) *                  Jumper J523 position 1-2 needs to be OPEN! ******************************************************************************** Revision History: Ver  Date         Author            Description of Changes 0.0  May-22-2019  David Tosenovjan  Initial version                            *******************************************************************************/

******************************************************************************** * Detailed Description: * Application performs basic initialization, setup PLL to maximum allowed freq., * initializes interrupts. STM_0 channel 0 is initialized to generate 100ms * periodic interrupt. Notice that STM is free running up counter, so it's * necessary to add calculated value to compare register each time in ISR handler. * * Test HW:         X-MPC5744PE257DC, MPC57xx motherboard * MCU:             SPC5744PGMMM9 1N15P * Fsys:            200 MHz * Debugger:        Lauterbach Trace32 *                  PeMicro USB-ML-PPCNEXUS * Target:          internal_FLASH (debug mode, release mode) * EVB connection:  User LED 1 connected to A0 (P8.0), * ********************************************************************************

******************************************************************************** * Detailed Description: * Application performs basic initialization, setup PLL to maximum allowed freq., * setup clock for peripherals, GPIO pins. * DSPI1 module is configured as a master, DSPI2 module is configured as a slave. * First, response of slave is initialized by writing to PUSHR register of DSPI2. * Second, we write PUSHR register of DSPI1 to send data from master. * Once data are received on both master and slave, data are read from POPR. * ------------------------------------------------------------------------------ * Test HW:         MPC5746R-176DC, MPC57xx Motherboard * MCU:             PPC5746R 1N83M * Fsys:            PLL 200MHz * Debugger:        Lauterbach Trace32 * IDE:             S32DS for Power 2017.R1 * Target:          internal_FLASH (debug mode, debug_ram mode) * EVB connection: * Connect PA13 (P8.14) to PS11 (P27.12) * Connect PA10 (P8.11) to PS10 (P27.11) * Connect PG12 (P14.13) to PS13 (P27.14) * Connect PG13 (P14.14) to PS7 (P27.8) * ********************************************************************************

******************************************************************************** * Detailed Description: * Test HW:  MPC57xx + S32R274RRUEVB * Maskset:  1N58R * Target :  internal_FLASH * Fsys:     240 MHz PLL with 40 MHz crystal reference for z7 and 120MHz for z4 ******************************************************************************** Revision History: 1.0     Apr-02-2019     b21190(Vlna Peter)  Initial Version 1.1    Apr-03-2019     b21190(Vlna Peter)  Added SWT reset reaction *******************************************************************************/ This example demonstrated the reset trigger on first SWT_2 timeout. Following screens shows the reset source after code execution in standalone mode and debugger connection afterwards:

* Detailed Description: * Test HW:  MPC57xx + S32R274RRUEVB * Maskset:  1N58R * Target :  internal_FLASH * Fsys:     240 MHz PLL with 40 MHz crystal reference for z7 and 120MHz for z4 * This example provides user with a configuration of clocks for all cores and all peripherals. * Peripherals and cores are supplied by maximum available clock configuration from PLLDIG block. ******************************************************************************** Revision History: 1.0     Apr-02-2019     b21190(Vlna Peter)  Initial Version *******************************************************************************/

******************************************************************************** Detailed Description: Configures the FlexCAN 0 to transmit and receive a CAN message  Baudrate to is set to 500kbps. In this config, RXFIFO is used to receive a messages. 16 filter elements are defined in the RXFIFO table. Both standard and extended IDs are used. MB10 is moreover used to receive a message with given standard ID. MB11 is used to transmit a message upon button press. The callback function is installed as well and is it called each time message is received in MB10, RXFIFO or message is transmitted. NOTE! Termination resistor (120Ohm) have to be placed on transceivers output             12V power supply must be connected. ------------------------------------------------------------------------------ Test HW: DEVKIT-MPC5748G Maskset: 0N78S Target : FLASH Fsys: 160 MHz PLL ********************************************************************************

******************************************************************************** * Detailed Description: * This example shows, how to use overlay feature - how to remap SRAM over Flash * and Flash over Flash. The remapping is visible only in mirrored flash address * space. Normal address space is not affected. To see effect of the remapping, * read the comments and watch following addresses in debugger before and after * executing Overlay() function: * * Flash over Flash test case: * 0x0104_0000 * 0x0108_0000 * 0x0904_0000 * 0x0908_0000 * * SRAM over Flash test case: * 0x4003_0000 * 0x090C_0000 * * ------------------------------------------------------------------------------ * Test HW:         DEVKIT-MPC5748G * MCU:             PPC5748GSMKU6 0N78S * Fsys:            PLL0 160MHz * Debugger:        Lauterbach Trace32 * Target:          internal_FLASH (debug mode) * EVB connection:  NA * ********************************************************************************

* Detailed Description: * This example demonstrates how to correctly execute ADC self-test for algorithm S and C. * -------------------------------------------------------------------------------------------------------------------- * Test HW:  MPC57xx EVB + MPC5744P minimodule * Maskset:  1N65H * Target :     internal_FLASH * Fsys:        200 MHz PLL with 40 MHz crystal reference ******************************************************************************** Revision History: 1.0     Apr-04-2016     b21190(Vlna Peter)  Initial Version *******************************************************************************/

******************************************************************************** * Detailed Description: * Application performs basic initialization, setup PLL to maximum allowed freq., * initializes interrupts and initializes software watchdog with window mode * allowed. Window mode is set for 2.5 ms. PIT timer is set to service SWT each * 8 ms, which is inside the window. * * * ------------------------------------------------------------------------------ * Test HW:         XPC560B 100LQFP, XPC56XX EVB MOTHEBOARD Rev.C * MCU:             PPC5604BE MLL 1M27V * Fsys:            64 MHz * Debugger:        Lauterbach Trace32 *                  PeMicro USB-ML-PPCNEXUS * Target:          RAM, internal_FLASH * EVB connection:   * ********************************************************************************

# README This is a mcan sdk demo on MPC5777C. Transmit data in turn and received data. CANFD is not used and extended id is used. Both Tx and Rx use interrupt. All documents are in [mpc5777c_test_mcan/mpc5777c_test_mcan_Z7_0/Documentation] folder. ## Board MPC5777C-416DS + MPC57xx MOTHERBOARD (SCH-27237 REV C) ## CAN PC Client PCAN-View ## Compiler powerpc-eabivle-gcc with S32 Design Studio for Power Architecture IDE ## MCAN MCAN0 ## Pin PC[19] - MCAN0 Tx PC[20] - MCAN0 Rx ## SDK S32_SDK_S32PA_EAR_1.8.0 ## Caution 1. Error to send data bytes which are not multiple times of 4 with MCAN_StartSendData() in mcan_driver.c. So MCAN_StartSendData() must be modified. Modified position is 606 to 607 lines in mcan_driver.c. 2. MCAN_DRV_InstallEventCallback() hasn't been implemented yet, must be added. ## Revision History Release 1.0.0 - 2018/12/19 - Jacob Peng - jacob.peng@nxp.com * Mod: MCAN_StartSendData() in mcan_driver.c * Add: MCAN_DRV_InstallEventCallback() in mcan_driver.c * Add: Demo application

******************************************************************************** * Detailed Description: * * Configures the MCANs to transmit and receive a CAN FD message with or without * bit rate switching for data phase. This is defined by BRS macro. * Baudrate during arbitration phase is set to 500kbps, during data phase 1Mpbs * because of PHY used on the EVB. * * In this config, MCAN_0 transmits a message. MCAN_1 receives the message. * * MCAN_0 sends message each 1sec. This interval is generated by PIT. * Single TX buffer is used to send n bytes. The message ID is changed for each * transmission. Two standard and 2 extended IDs are sent. * * MCAN_1 is configured to receive a message, ISR is used to read new message. * There are 2 standard and 2 extended ID filter tables defined. Classic filter * configuration is set, means filter ID & mask. * Messages with matched standard ID are received into RXFIFO_0, messages with matched * extended ID then stored in RXFIFO_1. * * EVB connection: * * J37 and J38 to position 2-3 to connect MCAN1 TX/RX to transceiver * * CAN0-CANH on P15-1 to CAN1-CANH on P14-1 * CAN0-CANL on P15-2 to CAN1-CANL on P14-2 * * * ------------------------------------------------------------------------------ * Test HW: MPC5777C-512DS Rev.D + MPC57xx MOTHER BOARD Rev.C * MCU: SPC5777CCMM03 3N45H * Fsys: PLL1 = core_clk = 264MHz, PLL0 = 192MHz * Debugger: Lauterbach Trace32 * Target: internal_FLASH * Terminal: 19200-8-no parity-1 stop bit-no flow control on eSCI_A * use USB connector (J21) on minimodule * * EVB connection: ETPUA30 (PortP P23-15) --> USER_LED_1 (P7-1) * ETPUA31 (PortP P23-14) --> USER_LED_2 (P7-2) * ********************************************************************************

MPC5744P FlexPWM offers possibility to synchronize the FlexPWM modules via external synchronization. Attached is example application how to properly synchronize 2 FlexPWMs modules: FlexPWMs run with motor control clock (MOT_CLK) with 100MHz frequency: PWM period is 20MHz with 50% duty cycle: Below is figure representing External synchronization of 2 PWM (on this frequency I have 2 clocks delay between synchronization) With adjusted FlexPWM0 channel A0 init value by 2 clocks I have reached following results:

******************************************************************************** * Detailed Description: * * LINFlexD_1 configured as Master *   - sends Header *   - either transmits a data to LIN Slave or receives data from a LIN Slave *   - no interrupt is used, just SW pooling * * LINFlexD_0 as Slave *   - receives header from a LIN Master *   - either receives data from a LIN Master or transmits a data to Master *   - filter is enabled *   - TX interrupt is used to prepare data to send and *   - RX interrupt to read received data * * EVB connection: * *   LIN1 circuitry *   connect 12V to LIN1-VSUP, so connect J23.1 to P11.3 *   J13, J12 jumpers placed * *   LIN0 circuitry *   remove J11 * *   connect LIN1 to LIN0, so connect P11 to P9 *   if do not have desired cable, connect P11.3-P9.3 and P11.4-P9.4 * *   See LIN signal on P11.4 or P9.4. * * ------------------------------------------------------------------------------ * Test HW:  X-MPC574xG-324DS + X-MPC574XG-MB * Maskset:  1N81M * Target :  FLASH * Fsys:     160 MHz PLL * ********************************************************************************