******************************************************************************** * Detailed Description: * Application performs basic initialization, setup PLL to maximum allowed freq., * start both Z7 cores, interrupts initialization, blinking three LED by interrupts, * initializes and display notice via UART terminal and then terminal ECHO. * Each core serves one interrupt and one LED. * * The example configures the device for maximum performance by initialization of * instruction/data cache and enabling of branch prediction for each core * (startup.s files). * * ------------------------------------------------------------------------------ * Test HW:         MPC5775K-356DS, MPC57xx Motherboard * MCU:             PPC5775KMMY3A 0N38M * Terminal:        19200-8-no parity-1 stop bit-no flow control on LINFlexD_0 * Fsys:            PLL0 266MHz *                    Z4 Core 133MHz *                    Both Z7 Cores 266MHz * Debugger:        Lauterbach Trace32 *                  PeMicro USB-ML-PPCNEXUS * Target:          internal_FLASH (debug mode, release mode) * EVB connection:  USER LED1 connected to P19.0, LED2 connected to P19.5 *                  LED3 connected to P19.8 *                  For correct UART functionality connect: *                  J14.2 to P12.6 *                  J13.2 to P12.7 * ********************************************************************************

******************************************************************************** * Detailed Description: * This example demostrates how to configure CGM )clock generation module) * and supply by clock all main peripherals. * * ------------------------------------------------------------------------------ * Test HW:  Test HW:  MPC57xx Motherboard + MPC5777M_512DS minimodule, MPC5777M, * Maskset:  0N75H * Target :  internal_FLASH * Fsys:     200 MHz PLL * ******************************************************************************** Revision History: 1.0     Nov-04-2014     b21190(Vlna Peter)  Initial Version 1.1     Feb-04-2016     b21190(Vlna Peter)  Fixed Clock configuration *******************************************************************************

This document describes the configuration, restrictions, principles and correct usage of FCCU module implemented on MPC5744P device. This document is preliminary release.

******************************************************************************** * Detailed Description: * Application performs basic initialization, setup PLL to maximum allowed freq., * initializes interrupts, blinking one LED by interrupt, * initializes and display notice via UART terminal and then terminal ECHO. * * * ------------------------------------------------------------------------------ * Test HW:         MPC5604EEVB64 * MCU:             PPC5604EEMLH 0N10D * Terminal:        19200-8-no parity-1 stop bit-no flow control on LINFLEX_0 * Fsys:            40 MHz * Debugger:        Lauterbach Trace32 *                  PeMicro USB-ML-PPCNEXUS * Target:          RAM, internal_FLASH * EVB connection:  JP17 connected to J38.7 (ADC CONN), jumpers J7,J8 position *                  2-3 fit SCI tx and rx connected * ********************************************************************************

******************************************************************************** * Detailed Description: * Application performs basic initialization, setup PLL1 to maximum allowed freq. PLL1 is system frequency, * PLL0 in initialized to 50MHz * initializes peripherals clock (MOTC_CLK is set to 5MHz) * initializes ETimer to count mode providing delay * initializes interrupts, blinking one LED by ETimer interrupt, * * * * Test HW:         X-MPC5744PE257DC, MPC57xx motherboard * MCU:             PPC5744PFMMM8 1N65H * Fsys:            200 MHz * Debugger:    Lauterbach Trace32 *                      PeMicro USB-ML-PPCNEXUS * Target:          internal_FLASH (debug mode, release mode) * EVB connection:  User LED 1 connected to A0 (P8.0), * * * ------------------------------------------------------------------------------

List of examples published by NXP technical support: MPC5 software example list * List of documents and tools published by NXP technical support: MPC5 document & tool list * * All of the source code placed in spaces above is for example use only. NXP does not accept liability for use of this code in the user’s application.

******************************************************************************** * Detailed Description: * Application performs basic initialization, setup PLL to maximum allowed freq., * initializes interrupts, blinking one LED by interrupt, * initializes and display notice via UART terminal and then terminal ECHO. * * You can choose TRK or Minimodule version using USED_BOARD macro * * ------------------------------------------------------------------------------ * Test HW:         XPC560P 100LQFP, XPC56XX EVB MOTHEBOARD Rev.B, TRK-MPC5604P Rev.B * MCU:             PPC5604PEFMLL 0M36W * Terminal:        19200-8-no parity-1 stop bit-no flow control on LINFLEX_0 * Fsys:            64/40 MHz * Debugger:        Lauterbach Trace32 *                  PeMicro USB-ML-PPCNEXUS * Target:          RAM, internal_FLASH * EVB connection:  Jumper J8 1st position fit LED1 connected to PE4, jumpers J22,23 position 2-3 fit SCI tx and rx connected * ********************************************************************************

******************************************************************************** * Detailed Description: * Application performs basic initialization, setup PLL to maximum allowed freq., * initializes interrupts, blinking one LED by interrupt, * initializes and display notice via UART terminal and then terminals ECHO. * * * Test HW:        X-MPC5744PE257DC, MPC57xx motherboard * MCU:              PPC5744PFMMM8 1N65H * Terminal:        19200-8-no parity-1 stop bit-no flow control on LINFlexD_0 * Fsys:             200 MHz * Debugger:      Lauterbach Trace32 *                       PeMicro USB-ML-PPCNEXUS * Target:          internal_FLASH (debug mode, release mode) * EVB connection:  User LED 1 connected to A0 (P8.0), * ********************************************************************************

******************************************************************************** * Detailed Description: * Application performs basic initialization, setup PLL to maximum allowed freq., * initializes interrupts, blinking one LED by interrupt, starts second core * initializes and display notice via UART terminal and then terminals ECHO. * * * Test HW:              MPC5688EVB * MCU:                   SPC5668GMMG 0N61C * Terminal:              19200-8-no parity-1 stop bit-no flow control on eSCI_A * Fsys:                   116 MHz * Debugger:             Lauterbach Trace32 *                             PeMicro USB-ML-PPCNEXUS * Target:                  RAM, internal_FLASH * EVB connection:   User LED 4 connected to pin P28-10 * *

******************************************************************************** * Detailed Description: * Application performs basic initialization, setup PLL to maximum allowed freq., * initializes interrupts, blinking one LED by interrupt, * initializes and display notice via UART terminal and then terminal ECHO. * ------------------------------------------------------------------------------ * Test HW:        XPC5604B 100LQFP, XPC56XX EVB MOTHEBOARD Rev.C * MCU:             PPC5604BE MLL 1M27V * Fsys:             64/48 MHz * Debugger:      Lauterbach Trace32 *                      PeMicro USB-ML-PPCNEXUS * Target:          internal_FLASH, (not enough memory for RAM target) * Terminal:       19200-8-no parity-1 stop bit-no flow control on LINFLEX_0 * EVB connection: default * ********************************************************************************

******************************************************************************** * Detailed Description: * Example show simple flash programming routine. During runtime it changes * content of field of constants 'test' (located in internal data flash). * Also it shows how to relocate data into FLASH (used linker command file * is MPC5675K_my_sections.lcf and MPC5675K_DEBUG_my_sections.lcf). * * Note: For complex tasks use SSD driver (Freescale site for particular device, * Software&Tools/Run-Time Software/Middleware-Device Drivers * ------------------------------------------------------------------------------ * Test HW:        MPC5675KEVB * MCU:            PPC5675KFMMSJ in Lock-Step mode * Fsys:           180/150 MHz CORE_CLK * Debugger:       Lauterbach Trace32 *                 PeMicro USB-ML-PPCNEXUS * Target:         RAM, internal_FLASH * Terminal:       19200-8-no parity-1 stop bit-no flow control on eSCI_A * EVB connection: default ********************************************************************************

******************************************************************************** * Detailed Description: * Application performs basic initialization, setup PLL to maximum allowed freq., * initializes interrupts, blinking one LED by interrupt, * initializes and display notice via UART terminal and then terminal ECHO. * ------------------------------------------------------------------------------ * Test HW:        XPC5607B 176LQFP, XPC56XX EVB MOTHEBOARD Rev.C * MCU:             PPC5607BMLUAM03Y * Fsys:             64/48 MHz * Debugger:      Lauterbach Trace32 *                      PeMicro USB-ML-PPCNEXUS * Target:           RAM, internal_FLASH * Terminal:       19200-8-no parity-1 stop bit-no flow control on LINFLEX_0 * EVB connection: default * ********************************************************************************

******************************************************************************** * Detailed Description: * * LINFlex UART TXFIFO transmit using DMA * LINFlex UART mode with FIFO receive using DMA * * * EVB connection: * *   Route LINFlexD_0 TXD/RXD (PB2/PB3) signals to the main board RS-232 transceiver *   Daughtercard: *   J17.11–12 ON  .. Connect LINFlexD_0 TXD (PB2) to main board. *   J17.8–9 ON .. Connect LINFlexD_0 RXD (PB3) to main board. * *   Motherboard *   J14 - SCI_RX ON *   J13 - SCI_TX ON *   J25 - SCI_PWR ON * * See results on PC terminal (baudrate 19200, Data bits 8, Stop bits 1, Parity none). * * ------------------------------------------------------------------------------ * Test HW:  MPC57xx * Maskset:  1N65H * Target :  internal_FLASH (debug mode, release mode without debugging information) * Fsys:     200 MHz PLL with 40 MHz crystal reference * Terminal: 19200, 8N1, None ********************************************************************************

******************************************************************************** * Detailed Description: * This example shows how to use eDMA for transfering 32-bit data multiple time using minor loop from internal flash to SRAM memory as well as how to configure AIPS (peripheral bridge) to grant eDMA access to peripherals. * * For closer details on how eDMA works I suggest you to check reference manual as this module is quite complex. * This example sets system clock for 200MHz running from PLL0 module. * The constant stored in internal flash is transfered via eDMA to SRAM memory. * Initialization functions are AIPS_0_Init for peripheral bridge and DMA_0_Init. * * ------------------------------------------------------------------------------ * Test HW:  MPC57xx Motherboard + MPC5744PE257DC minimodule, MPC5744P, * silicon mask set 0N15P * Target :  internal_FLASH* ********************************************************************************

******************************************************************************** * Detailed Description: * * CAN0 module is configured to transmit one message with ID 0x555 to CAN1 * module. CAN1 module is configured to use DMA to receive the message. * Once the DMA module reads the received frame, interrupt is triggered. * Follow application note AN4830 regarding the CAN settings. * http://www.freescale.com/files/microcontrollers/doc/app_note/AN4830.pdf * http://www.freescale.com/files/microcontrollers/doc/app_note/AN4830SW.zip * The example from AN4830 is modified to use DMA and RXFIFO on CAN1 module. * * ------------------------------------------------------------------------------ * Test HW:  MPC57xx * Maskset:  1N81M * Target :  SRAM * Fsys:     160 MHz PLL * ********************************************************************************

******************************************************************************** * Detailed Description: * Application performs basic initialization, initializes interrupts, blinking * one LED by Core0, second by Core1 (by interrupt), initializes and display * notice via UART terminal and then terminal ECHO. * * ------------------------------------------------------------------------------ * Test HW:         MPC5777C-512DS Rev.A + MPC57xx MOTHER BOARD Rev.C * MCU:             PPC5777CMM03 2N45H CTZZS1521A * Fsys:            PLL1 = core_clk = 264MHz, PLL0 = 192MHz * Debugger:        Lauterbach Trace32 * Target:          internal_FLASH * Terminal:        19200-8-no parity-1 stop bit-no flow control on eSCI_A * EVB connection:  ETPUA30 (PortP P23-15) --> USER_LED_1 (P7-1) *                  ETPUA31 (PortP P23-14) --> USER_LED_2 (P7-2) * ********************************************************************************

******************************************************************************** * Detailed Description: * This example initializes SMPU_0 and SMPU_1 to cover all memory resources for * all masters. * Simple test case is used in this example: after initialization, SMPU * configuration is changed to disable write access to last 4kB of RAM. * Once this area is written by CPU, exception will occur due to access * violation. * ------------------------------------------------------------------------------ * Test HW:  MPC57xx * Maskset:  1N81M * Target :  SRAM * Fsys:     160 MHz PLL * ********************************************************************************

******************************************************************************** * Detailed Description: * Purpose of the example is to show how to generate Multi-bit or Single-bit * ECC error in internal SRAM (user must choose it in the option at the end of * main function). * Error Injection Module is used to generate a non-correctable (or single-bit) * ECC error in RAM. The bad data is accessed then, so the IVOR1 exception (or * ERM combined interrupt service routine) is generated and handled. * Example also offers useful macros for EIM and ERM modules. * The example displays notices in the terminal window (USBtoUART bridge J21) * (19200-8-no parity-1 stop bit-no flow control on eSCI_A). * No other external connection is required. * * ------------------------------------------------------------------------------ * Test HW:         MPC5777C-512DS Rev.A + MPC57xx MOTHER BOARD Rev.C * MCU:             PPC5777CMM03 2N45H CTZZS1521A * Fsys:            PLL1 = core_clk = 264MHz, PLL0 = 192MHz * Debugger:        Lauterbach Trace32 * Target:          internal_FLASH * Terminal:        19200-8-no parity-1 stop bit-no flow control on eSCI_A * EVB connection:  eSCI_A is USBtoUART bridge (connector J21) * ********************************************************************************

This config tool simplifies PLL setting calculation and clock configuration for MPC5744P device.                  Follow these steps                  Note: Macros have to be enabled!                  1. Enter frequency of used XOSC and desired PLL0 and PLL1 output.                 - put values into cells B11, Q10 and Q17 of the "Clocks" sheet                 - check if it is Valid or Invalid                 - "PLLconfig" sheet shows possible PLLs configurations                  2. Configure System and AUX clock selectors and its Dividers                 - check calculated frequency of System/Peripheral clocks                 - if Invalid change source clock and Divider value to keep Max freq                    3. Copy generated code by pressing "Copy Code" button

******************************************************************************** * Detailed Description: * * * This example shows usage of FlexPWM and Sine Wave generator (SGEN) modules. * The setting is selected in the way to have a PWM output signal synhronized with * SWG output signal. This is necessary for resolver usage in motor control appls. * The CTU_0 is triggered from FlexPWM_0's. The PMWB output rising edge is used here. * The CTU generates the eTIMER1_TRG signal, that is a trigger signal for the * SGEN module. The delay between PWMB and SGEN trigger is changed so you can see * the generated sinusoidal signal change phase against the PWMB output. * * See attached Excel sheet for calculation of parammeters used here (AUX0_clk_DIV0, * AUX0_clk_DIV1, SGEN_IOFREQ, PWM_PRESCALER, PWM_MODULO). * * This example is set for 9.765625KHz SGEN/PWM frequency. * * Note  because the SGEN trigger input is an asynchronous signal, it must be held high * for at least 2 SGEN clock cycles in order to capture the input trigger. * As the CTU generates the trigger as a pulse of single CTU clock width, the CTU clock must be * half of the SGEN clock at least. * * Use the AUX0_clk_DIV0 to test this behaviour. * * * ------------------------------------------------------------------------------ * Test HW:  MPC57xx * Maskset:  1N65H * Target :  internal_FLASH * Fsys:     200 MHz PLL with 40 MHz crystal reference * * EVB connection: * * P11.8 - D[7] .. SGEN output *          connected to FEC PHY's MIIMODE input on motherboard, *          to see full amplitude remove J26    * * P8.12    - A[11] .. FlexPWM A[0] output * P8.11    - A[10] .. FlexPWM B[0] output * * ********************************************************************************