******************************************************************************** * Detailed Description: * Initializes eQADC module, converts specified command queue and displays * results into terminal window when EOQ is reached. Used analog inputs ANA_0 and * ANA_1 requires external connection to converted voltage (potentiometer) to * see some valid numbers. For simplicity, ADC module is not calibrated. * ------------------------------------------------------------------------------ * Test HW:         XPC567XKIT516 - MPC5674ADAT516 Rev.C, MPC567XEVBFXMB Rev.B * MCU:             PPC5674FMVYA264 * Terminal:        19200-8-no parity-1 stop bit-no flow control on eSCI_A * Fsys:            264/200/150/60 MHz * Debugger:        Lauterbach Trace32 *                  PeMicro USB-ML-PPCNEXUS * Target:          RAM, internal_FLASH * EVB connection:  Potentiometers     --> ADC inputs *                  USER_DEV_RV2(J4-7) --> ANA_0 (J18-3) *                  USER_DEV_RV3(J4-8) --> ANA_1 (J18-4)                * ********************************************************************************

******************************************************************************** * Detailed Description: * Application performs basic initialization, setup PLL to maximum allowed freq. * DSPI_A is configured as master, DSPI_B is configured as slave. * DSPI modules are connected together by wires on EVB. * Four DMA descriptors are initialized: * - master transmit * - master receive * - slave transmit * - slave receive * All transfers are done by DMA, master sends/receives 8 words and slave * receives/sends 8 words. * ------------------------------------------------------------------------------ * Test HW:         XPC567XKIT516 - MPC567xADAT516 Rev.D, MPC567XEVBFXMB Rev.C * MCU:             PPC5676RDMVY1 3N23A * Fsys:            180MHz * Debugger:        Lauterbach Trace32 * Target:          RAM, internal_FLASH * EVB connection:  PCSA0 (J29-1) -> PCSB0 (J30-1) *                  SIN_A (J29-7) -> SOUT_B (J30-8) *                  SOUT_A (J29-8) -> SIN_B (J30-7) *                  SCK_A (J29-9) -> SCK_B (J30-9) * ********************************************************************************

******************************************************************************** * Detailed Description: * Initializes eQADC module, performs calibration and converts channel 0 and * displays results into terminal window by interrupt service routine. Analog * input AN[0] requires external connection to converted voltage (potentiometer). * ------------------------------------------------------------------------------ * Test HW:        MPC5554EVB * MCU:            MPC5554MVR132 * Fsys:           132/112/80/12 MHz * Debugger:       Lauterbach Trace32 *                 PeMicro USB-ML-PPCNEXUS * Target:         RAM, internal_FLASH * Terminal:       19200-8-no parity-1 stop bit-no flow control on eSCI_A * EVB connection: USER_DEV pin RV2(i.e. pin8) -> pin B7 on I/O header ring *                 (potentiometer RV2 to analog input AN[0])   * ********************************************************************************

******************************************************************************** * Detailed Description: * MPU is initialized to cover all resources (flash, RAM, peripheral bridges). * All masters are allowed to read-write-execute from all resources. * * Simple test case is used to check the behavior of MPU in case of access * violation: * - the MPU is reconfigured to disable write access to first 1KB or RAM memory *   (0x4000_0000 - 0x4000_03FF). * - if we write this RAM area, machine check exception is triggered * ------------------------------------------------------------------------------ * Test HW:         XPC567XKIT516 - MPC5674ADAT516 Rev.C, MPC567XEVBFXMB Rev.B * MCU:             PPC5674FMVYA264 * Fsys:            264MHz * Debugger:        Lauterbach Trace32 * Target:          RAM, internal_FLASH * ********************************************************************************

Detailed Description:  Initializes the MCU including the FlexCAN peripherals.  Configures the FlexCAN to transmit and receive a CAN message.  In this config, CAN_0 transmits a message. CAN_1 receives the message.  CAN_0 MB8 is configured to send data each 1sec.This interval is generated by PIT.  CAN_1 RXFIFO is configured to receive a message and interrupt for MB5 is enabled.  To connect FlexCAN0 module (MCU's PB0/PB1 pins) to the motherboard's transceiver  with J5 CAN DB9 connector you have to:  - connect J17 2-6 on daughter board  - connect J17 5-3 on daughter board  This should be done as default    To connect FlexCAN1 module (MCU's PA14/PA15 pins) to the motherboard's transceiver  with J6 CAN DB9 connector you have to:  - connect J37 2-3 on motherboard  - connect J38 2-3 on motherboard  Connect CAN0-CANH on P15-1 to CAN1-CANH on P14-1  Connect CAN0-CANL on P15-2 to CAN1-CANL on P14-2  Terminate the CAN bus by connecting a 60 ohm resistor between CANH and CANL  To see LED toggling connect P8.1 to USER LED (P7.x)  ------------------------------------------------------------------------------  Test HW:  MPC5744P EVB  Maskset:  1N65H  Target :  RAM, internal_FLASH  Fsys:     200 MHz PLL with 40 MHz crystal reference

******************************************************************************** * Version:          1.0 * Date:             Oct-22-2014 * Classification:   General Business Information * Brief:        This example demonstrate SWT functionality *                 On SWT timeout it sent signal to FCCU where is long *                 functional reset reaction on SWT timeout configured *                 FCCU then sent signal to RGM module which triggers long *                 functional reset. ******************************************************************************** * Test HW:  MPC57xx * Maskset:  1N65H * Target :  internal_FLASH * Fsys:     200 MHz PLL with 40 MHz crystal reference ******************************************************************************** Revision History: 1.0     Oct-22-2014     b21190(Vlna Peter)  Initial Version 1.1     Mar-24-2015    b21190(Vlna Peter)  Added SWT long reset *******************************************************************************/

******************************************************************************** * Detailed Description: * Example demonstates Shifted PWM generating via eMIOS. * The shift is 25% duty cycle. * ------------------------------------------------------------------------------ * Test HW:  MPC5644A + XPC564A minimodule + XPC56XX mother board * Maskset:  OM14X * Target :  Internal Flash * Fsys:     16MHz IRC * * EVB settings: * PJ8 pin 0 is eMIOS CH[0] * PJ8 pin 2 is eMIOS CH[2] ******************************************************************************** Revision History: 1.0     Jun-23-2016     b21190(Vlna Peter)  Initial Version *******************************************************************************/

******************************************************************************** * Detailed Description: * This example content a basic PMPLL initialization and *  configuration of Mode Entry module and Clock Generation *  module for core1 and start of core0 and core0s from Core_Init function. * Also containts Lauterbach multicore multi-Trace32 view script for multicore * debugging puproses ******************************************************************************** * Test HW:  Test HW:  MPC57xx Motherboard + MPC5777M_512DS minimodule, MPC5777M, * Test HW:  MPC57xx * Maskset:  1N83M (cut 2.0B) * Target :  internal_FLASH * Fsys:     200MHz PLL0 as system clock ******************************************************************************** Revision History: 1.0     Jun-09-2015     b21190(Vlna Peter)  Initial Version 1.1     Sep-20-2016     b21190(Vlna Peter)  core0+core0s boot function added *******************************************************************************

******************************************************************************** * Detailed Description: * * Configures the MCANs to transmit and receive a CAN message. * * In this config, MCAN_1 transmits a message. MCAN_2 receives the message. * * MCAN_1 sends message each 1sec. This interval is generated by PIT. * Single TX buffer is used to send n bytes. The message ID is changed for each * transmission. Two standard and 2 extended IDs are sent. * * MCAN_2 is configured to receive a message, SW polling is used. * There are 2 standard and 2 extended ID filter tables defined. Classic filter * configuration is set, means filter ID & mask. * Messages with matched standard ID are received into RXFIFO_0, messages with matched * extended ID then stored in RXFIFO_1. *   * EVB connection: * * J37 and J38 to position 1-2 to connect MCAN1 TX/RX to transceiver * * CAN0-CANH on P15-1 to CAN1-CANH on P14-1 * CAN0-CANL on P15-2 to CAN1-CANL on P14-2 * * ------------------------------------------------------------------------------ * Test HW:  MPC5777M, MPC57xx Motherboard + MPC5777M_512DS minimodule * Maskset:  0N78H * Target :  internal_FLASH * Fsys:     600 MHz PLL1 with 40 MHz crystal reference, *        core2 at 200MHz generated from PPL1 * Terminal: None ******************************************************************************** Revision History: 1.0     Jan-5-2017     PetrS    Initial Version of MCAN example *******************************************************************************/

******************************************************************************** * Detailed Description: * Basic initialization of CMPU: * Region 0 (Instruction): Internal Flash @ 0x0040_0000-0x01FF_FFFF * Region 1 (Instruction): SRAM   @ 0x4000_0000-0x4005_FFFF * Region 6 (Data): SRAM @ 0x4000_0000-0x4005_FFFF * Region 7 (Data): Internal Flash @ 0x0040_0000-0x011F_FFFF * Region 8 (Data): PBRIDGE1/0 @ 0xF800_0000-0xFFFF_FFFF * * This excel configurator has been used: * https://community.nxp.com/docs/DOC-335467 * * ------------------------------------------------------------------------------ * Test HW:         X-MPC5744PE257DC, MPC57xx motherboard * MCU:             PPC5744PFMMM8 1N65H * Fsys:            200 MHz PLL * Debugger:        Lauterbach Trace32 * Target:          internal_FLASH * ********************************************************************************

******************************************************************************** * Detailed Description: * Application performs basic initialization, setup PLL to maximum allowed freq., * start one Z7 core, interrupts initialization, ICache and DCache are disabled * on both cores because of shared memory, which must not be cached. * * There is 4K shared memory defined in the linker file. This memory is used by * both cores. Both cores access into the structure, which is placed in the shared * memory. This access is marked as a critical section. Only one core can write * to the structure at the same time. To ensure this, there are Gates, which * guarantee data coherence during the access. Only one core can be in critical * section. Second core has to wait, until first core leaves the critical section * * * * ------------------------------------------------------------------------------ * Test HW:         MPC5775K-356DS, MPC57xx Motherboard * MCU:             PPC5775KMMY3B 0N76P * Terminal:        19200-8-no parity-1 stop bit-no flow control on LINFlexD_0 * Fsys:            PLL0 266MHz *                    Z4 Core 133MHz *                    Z7 Core 266MHz * Debugger:        Lauterbach Trace32 *                  PeMicro USB-ML-PPCNEXUS * Target:          internal_FLASH (debug mode, release mode) * EVB connection:  default connection * ********************************************************************************

******************************************************************************** * Detailed Description: * This example shows how to use eDMA for transfering 32-bit data multiple time using minor loop from internal flash to SRAM memory as well as how to configure AIPS (peripheral bridge) to grant eDMA access to peripherals. * * For closer details on how eDMA works I suggest you to check reference manual as this module is quite complex. * This example sets system clock for 200MHz running from PLL0 module. * The constant stored in internal flash is transfered via eDMA to SRAM memory. * Initialization functions are AIPS_0_Init for peripheral bridge and DMA_0_Init. * * ------------------------------------------------------------------------------ * Test HW:  MPC57xx Motherboard + MPC5744PE257DC minimodule, MPC5744P, * silicon mask set 0N15P * Target :  internal_FLASH* ********************************************************************************

******************************************************************************** * Detailed Description: * Application performs basic initialization, setup PLL to maximum allowed freq., * setup clock for peripherals, setup access right for Masters and Peripherals * on AIPS_0 * * DMA transfers block of data from variable TransmitBuffer to the variable * ReceiveBuffer. Both variables are placed in SRAM. * * ICache and DCache are both disabled in startup file using CACHE_ENABLE macro. * You can change the value of the macro at the following path: * project Properties/C/C++ General/Paths and Symbols/Symbols * If you change the value to 1, ICahce and DCache will be enabled in startup. * * * ------------------------------------------------------------------------------ * Test HW:         MPC5775K-356DS, MPC57xx Motherboard * MCU:             PPC5775KMMY3A 0N38M * Fsys:            PLL0 266MHz *                    Z4 Core 133MHz * Debugger:        Lauterbach Trace32 *                  PeMicro USB-ML-PPCNEXUS * Target:          internal_FLASH (debug mode, release mode) * EVB connection:  default * ********************************************************************************

******************************************************************************** * Detailed Description: * This example shows how to use FCCU module for fake fault injection in order to test FCCU functionality. * * For closer details on how FCCU works I suggest you to check reference manual as this module is quite complex. * This example sets system clock for 200MHz running from PLL0 module. * The FCCU_Fake_fault_inject function is setting and injecting FCCU fault NCF[7] - STCU2 fault condition. * Short reset is triggered as soon as FCCU registers injected fault. * * ------------------------------------------------------------------------------ * Test HW:  MPC57xx Motherboard + MPC5744PE257DC minimodule, MPC5744P, * silicon mask set 1N65H * Target :  internal_FLASH* ********************************************************************************

******************************************************************************** * Detailed Description: * * eQADC mode: Continuous scan with external trigger. * Periodic trigger from eMIOS_0 ch16. * ANA ch5 is converted and result is sent to RFIFO0. * * eMIOS ch0 duty cycle is modified based on result data, so LED is dimming * if connected to eMIOS ch0 output. * * ADC result is also displayed on terminal each second. * * ------------------------------------------------------------------------------ * Test HW:         MPC5777C-512DS Rev.A + MPC57xx MOTHER BOARD Rev.C * MCU:             PPC5777CMM03 2N45H CTZZS1521A * Fsys:            PLL1 = core_clk = 264MHz, PLL0 = 192MHz * Debugger:        Lauterbach Trace32 * Target:          internal_FLASH * Terminal:        19200-8-no parity-1 stop bit-no flow control on eSCI_A *           use USB connector (J21) on minimodule * * EVB connection:  ETPUA30 (PortP P23-15) --> USER_LED_1 (P7-1) *                  ETPUA31 (PortP P23-14) --> USER_LED_2 (P7-2) * *           eMIOS ch0 (PortG P14-16)--> USER_LED_4 (P7-4) *                  ANA0       (PortQ P24-5) --> RV1 (J53.1) * ********************************************************************************

******************************************************************************** * Detailed Description: * Application performs basic initialization, setup PLL to maximum allowed freq., * initializes interrupts, blinking one LED by interrupt, * initializes and display notice via UART terminal and then terminal ECHO. * * * ------------------------------------------------------------------------------ * Test HW:         MPC5604EEVB64 * MCU:             PPC5604EEMLH 0N10D * Terminal:        19200-8-no parity-1 stop bit-no flow control on LINFLEX_0 * Fsys:            40 MHz * Debugger:        Lauterbach Trace32 *                  PeMicro USB-ML-PPCNEXUS * Target:          RAM, internal_FLASH * EVB connection:  JP17 connected to J38.7 (ADC CONN), jumpers J7,J8 position *                  2-3 fit SCI tx and rx connected * ********************************************************************************

This document describes how to use On-line BISTs on MPC5777C. --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- STCU2 On-line BIST (MBIST+ LBIST) execution time on NXP Evaluation board ( X-MPC5777C-561DS) is 25.8ms. This measured time is valid for: System clock PLL = 200MHz STCU module clock = System clock / 4 MBIST = 50MHz LBIST = 25MHz Result after testing MBIST+LBIST = 0 faults latched in ERR_STAT register and all LBISTs was successfully executed. --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- STCU2 On-line LBIST only execution time on NXP Evaluation board ( X-MPC5777C-561DS) is 37.4ms. This measured time is valid for: System clock PLL = 200MHz STCU module clock = System clock / 4 LBIST = 25MHz --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- LBIST on 50MHz I do not recommend to run LBIST at 50MHz as it was failing in my setup.

# README This is a mcan sdk demo on MPC5777C. Transmit data in turn and received data. CANFD is not used and extended id is used. Both Tx and Rx use interrupt. All documents are in [mpc5777c_test_mcan/mpc5777c_test_mcan_Z7_0/Documentation] folder. ## Board MPC5777C-416DS + MPC57xx MOTHERBOARD (SCH-27237 REV C) ## CAN PC Client PCAN-View ## Compiler powerpc-eabivle-gcc with S32 Design Studio for Power Architecture IDE ## MCAN MCAN0 ## Pin PC[19] - MCAN0 Tx PC[20] - MCAN0 Rx ## SDK S32_SDK_S32PA_EAR_1.8.0 ## Caution 1. Error to send data bytes which are not multiple times of 4 with MCAN_StartSendData() in mcan_driver.c. So MCAN_StartSendData() must be modified. Modified position is 606 to 607 lines in mcan_driver.c. 2. MCAN_DRV_InstallEventCallback() hasn't been implemented yet, must be added. ## Revision History Release 1.0.0 - 2018/12/19 - Jacob Peng - jacob.peng@nxp.com * Mod: MCAN_StartSendData() in mcan_driver.c * Add: MCAN_DRV_InstallEventCallback() in mcan_driver.c * Add: Demo application

This example performs LED toggling using hardware vector mode.   *UPDATE* - Internal RAM function was added, fixed exceptions, * * Detailed Description: * - 1 second LED1 toggle using emios interrupt * - LED2 toggle using irq 0 interrupt via sw_button1 * - 1 second LED3 toggle using Decrementer via IVOR10 * - hardware vector mode configuration for interrupts * * ------------------------------------------------------------------------------ * Test HW:  MPC5566 EVB MOTHERBOARD, PPC5566 MVR132 * Target :  Internal Flash, Internal RAM * Fsys:     80 MHz PLL with 8 MHz crystal reference * * ------------------------------------------------------------------------------ * EVB connections and jumper configuration * * MPC5566 EVB MOTHERBOARD * * LED1 D17 * LED2 A17 * LED3 C16 * For SW1 is used pin 2 and it is connected to AF19 * *********************************************************************************

******************************************************************************** * Version:          1.0 * Date:             Oct-22-2014 * Classification:   General Business Information * Brief:         This example demonstrate SWT functionality *                   On SWT timeout it sent signal to FCCU where is short *                   functional reset reaction on SWT timeout configured *                   FCCU then sent signal to RGM module which triggers short *                   functional reset. ******************************************************************************** * Test HW:  MPC57xx * Maskset:  1N65H * Target :  internal_FLASH * Fsys:     200 MHz PLL with 40 MHz crystal reference ******************************************************************************** Revision History: 1.0     Oct-22-2014     b21190(Vlna Peter)  Initial Version 1.1        Mar-24-2015       b21190(Vlna Peter)  Added SWT short reset *******************************************************************************/