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******************************************************************************** * Detailed Description: * Application performs basic initialization, setup PLL to maximum allowed freq., * start both Z7 cores, interrupts initialization, blinking three LED by interrupts, * initializes and display notice via UART terminal and then terminal ECHO. * Each core serves one interrupt and one LED. * * The example configures the device for maximum performance by initialization of * instruction/data cache and enabling of branch prediction for each core * (startup.s files). * * ------------------------------------------------------------------------------ * Test HW: MPC5775K-356DS, MPC57xx Motherboard * MCU: PPC5775KMMY3A 0N38M * Terminal: 19200-8-no parity-1 stop bit-no flow control on LINFlexD_0 * Fsys: PLL0 266MHz * Z4 Core 133MHz * Both Z7 Cores 266MHz * Debugger: Lauterbach Trace32 * PeMicro USB-ML-PPCNEXUS * Target: internal_FLASH (debug mode, release mode) * EVB connection: USER LED1 connected to P19.0, LED2 connected to P19.5 * LED3 connected to P19.8 * For correct UART functionality connect: * J14.2 to P12.6 * J13.2 to P12.7 * ********************************************************************************

Detailed Description: Demo application measures analog voltage from externally connected humidity sensor HIH-5030. Obtained values and processed and displayed on MPC5606S-DEMO-V2 board’s TFT panel. Application uses standard Graphics Libraries for MPC5606S for simple graphic output that is managed in mc_base.c module only. ------------------------------------------------------------------------------ Test HW: MPC5606S-DEMO-V2 + HIH-5030 MCU: PPC5606SEF OMLU 0M25V DD68391 XOTAC1003 Fsys: 64MHz Debugger: Lauterbach Trace32 Target: internal_FLASH Terminal: none EVB connection: For complete project you may see following link: Demo application MPC5606S-DEMO + LM75B + HIH-5030 + PCA8565 + GUI

******************************************************************************** * Detailed Description: * Purpose of the example is to show how to generate Multi-bit or Single-bit ECC * error in internal RAM (user must choose it in the option at the end of main * function). * ECC fault is generated with using of core register E2EECSR. If error injection * is enabled (E2EECSR0[INVC]=1) and certain mask is set (E2EECSR0[CHKINVT]), * subsequent write to SRAM creates error in SRAM array. * When corrupted data is read the IVOR1 exception handler is called in case of * multi-bit ECC error (IVOR1 exception occurs) and FCCU_Alarm_Interrupt handler * is called in case of single-bit ECC error (FCCU interrupt occurs). * Both function calls MEMU handler. * The example displays notices in the terminal window (connector J19 on * MPC57xx_Motherboard)(19200-8-no parity-1 stop bit-no flow control on eSCI_A). * No other external connection is required. * ------------------------------------------------------------------------------ * Test HW: MPC57xx_Motherboard + MPC5744P-144DC * MCU: PPC5744PFMLQ8,0N15P,QQAA1515N, Rev2.1B * Fsys: 200 MHz PLL with 40 MHz crystal reference * Debugger: Lauterbach Trace32 * Target: internal_FLASH, RAM * Terminal: 19200-8-no parity-1 stop bit-no flow control * EVB connection: default ********************************************************************************

******************************************************************************** * Detailed Description: * This example initializes SMPU_0 and SMPU_1 to cover all memory resources for * all masters. * Simple test case is used in this example: after initialization, SMPU * configuration is changed to disable write access to last 4kB of RAM. * Once this area is written by CPU, exception will occur due to access * violation. * ------------------------------------------------------------------------------ * Test HW: MPC57xx * Maskset: 1N81M * Target : SRAM * Fsys: 160 MHz PLL * ********************************************************************************

******************************************************************************** * Detailed Description: * * * This example shows usage of FlexPWM and Sine Wave generator (SGEN) modules. * The setting is selected in the way to have a PWM output signal synhronized with * SGEN output signal. This is necessary for resolver usage in motor control appls. * * See attached Excel sheet for calculation of parammeters used here (AUX0_clk_DIV0, * AUX0_clk_DIV1, SGEN_IOFREQ, PWM_PRESCALER, PWM_MODULO). * * This example is set for 2.44140625 kHz SGEN/PWM frequency. * * * ------------------------------------------------------------------------------ * Test HW: MPC57xx * Maskset: 1N65H * Target : internal_FLASH * Fsys: 200 MHz PLL with 40 MHz crystal reference * * EVB connection: * * P20.1 - D[7] .. SGEN output * connected to FEC PHY's MIIMODE input on motherboard, * to see full amplitude remove J26 * * P8.12 - A[11] .. FlexPWM A[0] output * P8.11 - A[10] .. FlexPWM B[0] output * * ********************************************************************************

******************************************************************************** * Detailed Description: * Application performs basic initialization, setup PLL to maximum allowed freq., * initializes interrupts, blinking one LED by interrupt, * initializes and display notice via UART terminal and then terminal ECHO. * * You can choose TRK or Minimodule version using USED_BOARD macro * * ------------------------------------------------------------------------------ * Test HW: XPC560P 100LQFP, XPC56XX EVB MOTHEBOARD Rev.B, TRK-MPC5604P Rev.B * MCU: PPC5604PEFMLL 0M36W * Terminal: 19200-8-no parity-1 stop bit-no flow control on LINFLEX_0 * Fsys: 64/40 MHz * Debugger: Lauterbach Trace32 * PeMicro USB-ML-PPCNEXUS * Target: RAM, internal_FLASH * EVB connection: Jumper J8 1st position fit LED1 connected to PE4, jumpers J22,23 position 2-3 fit SCI tx and rx connected * ********************************************************************************

* Detailed Description: * Test HW: MPC57xx + S32R274RRUEVB * Maskset: 1N58R * Target : internal_FLASH * Fsys: 240 MHz PLL with 40 MHz crystal reference for z7 and 120MHz for z4 * This example provides user with a configuration of clocks for all cores and all peripherals. * Peripherals and cores are supplied by maximum available clock configuration from PLLDIG block. ******************************************************************************** Revision History: 1.0 Apr-02-2019 b21190(Vlna Peter) Initial Version *******************************************************************************/

******************************************************************************** * Detailed Description: * * LINFlexD_1 configured as Master * - sends Header * - either transmits a data to LIN Slave or receives data from a LIN Slave * - no interrupt is used, just SW pooling * * LINFlexD_0 as Slave * - receives header from a LIN Master * - either receives data from a LIN Master or transmits a data to Master * - filter is enabled * - TX interrupt is used to prepare data to send and * - RX interrupt to read received data * * EVB connection: * * LIN1 circuitry * connect 12V to LIN1-VSUP, so connect J23.1 to P11.3 * J13, J12 jumpers placed * * LIN0 circuitry * remove J11 * * connect LIN1 to LIN0, so connect P11 to P9 * if do not have desired cable, connect P11.3-P9.3 and P11.4-P9.4 * * See LIN signal on P11.4 or P9.4. * * ------------------------------------------------------------------------------ * Test HW: X-MPC574xG-324DS + X-MPC574XG-MB * Maskset: 1N81M * Target : FLASH * Fsys: 160 MHz PLL * ********************************************************************************

This demo performs a communication on LIN bus between two MPC5604B EVBs. LinFlex0 LIN Master ******************************************************************************** * Detailed Description: * - send header from a LIN Master * - either receive data from a LIN Slave or transmit a data * - no interrupt is used, just SW pooling * * ------------------------------------------------------------------------------ * Test HW: XPC560B 144 LQFP MINIMODULE, XPC56XX EVB MOTHERBOARD, SPC5604B 2M27V * Target : internal_RAM, Flash * LinFlex0: Lin Master, 19200 baudrate * Fsys: 64 MHz PLL with 8 MHz crystal reference * * ------------------------------------------------------------------------------ * EVB connections and jumper configuration * * XPC56XX EVB MOTHERBOARD * for LinFlex0 connection to the MC33661 LIN transceiver: * - RXDA_SEL (near SCI !!!!) jumper over pins 1-2 * - TXDA_SEL (near SCI) jumper over 1-2 * * for LIN Master functionality * - VSUP (J6) jumper fitted * lin xceiver will get +12V from the EVB * - V_BUS (J14) jumper not fitted * - MASTER_EN jumper fitted * - LIN_EN jumper fitted * ******************************************************************************** LinFlex0 LIN Slave ******************************************************************************** * Detailed Description: * - receive header from a LIN Master * - either receive data from a LIN Master or transmit a data * - Filter can be enabled with the FILT_EN = 1 * - If filter is enabled TX interrupt is used to prepare data to send and * RX interrupt to read received data * - If filter is disabled SW polling is used * * ------------------------------------------------------------------------------ * Test HW: XPC560B 144 LQFP MINIMODULE, XPC56XX EVB MOTHERBOARD, SPC5604B 2M27V * Target : internal_RAM * LinFlex0: Lin Slave, 19200 baudrate * Fsys: 64 MHz PLL with 8 MHz crystal reference * * ------------------------------------------------------------------------------ * EVB connections and jumper configuration * * XPC56XX EVB MOTHERBOARD * for LinFlex0 connection to the MC33661 LIN transceiver: * - RXDA_SEL (near SCI !!!!) jumper over pins 1-2 * - TXDA_SEL (near SCI) jumper over pins 1-2 * * for LIN Slave functionality * - VSUP (J6) jumper not fitted ...LIN transceiver will get +12V from the Master * - V_BUS jumper not fitted * - MASTER_EN jumper not fitted * - LIN_EN jumper fitted * ********************************************************************************

******************************************************************************** * Detailed Description: * Purpose of the example is to show how to generate Multi-bit ECC error in * local DMEM memory. * ECC fault is generated with using of core register DMEMCTL0. If error * injection is enabled (DMEMCTL0[DPEIE]=1), subsequent write to DMEM creates * 2b ECC error in DMEM array and following read of this area causes bus error * (IVOR1 exception) or FCCU_Alarm_Interrupt. * Both function calls MEMU handler. * Example does not show any handling as it is application specific. * The example displays notices in the terminal window (connector J19 on * MPC57xx_Motherboard)(19200-8-no parity-1 stop bit-no flow control on eSCI_A). * No other external connection is required. * ------------------------------------------------------------------------------ * Test HW: MPC57xx_Motherboard + MPC5744P-144DC * MCU: PPC5744PFMLQ8,0N15P,QQAA1515N, Rev2.1B * Fsys: 200 MHz PLL with 40 MHz crystal reference * Debugger: Lauterbach Trace32 * Target: internal_FLASH, RAM * Terminal: 19200-8-no parity-1 stop bit-no flow control * EVB connection: default ********************************************************************************

******************************************************************************** * Detailed Description: * Application performs basic initialization, initializes interrupts and external * interrupt for IRQ0 pin (alternative function of ETPUC9 pin). * User needs to connect ETPUC9 pin to user switch and general purpose output * ETPUA30 to user LED 1: * ETPUA30 (PortP P23-15) --> USER_LED_1 (P7-1) * ETPUC9 (PortV P30-8) --> USER_SWITCHES (P6-4) * * If rising edge is detected (i.e. button is pressed), interrupt is triggered * and LED1 on is toggled. * * ------------------------------------------------------------------------------ * Test HW: MPC5777C-512DS Rev.A + MPC57xx MOTHER BOARD Rev.C * MCU: PPC5777CMM03 2N45H CTZZS1521A * Fsys: PLL1 = core_clk = 264MHz, PLL0 = 192MHz * Debugger: Lauterbach Trace32 * Target: internal_FLASH * Terminal: 19200-8-no parity-1 stop bit-no flow control on eSCI_A * EVB connection: ETPUA30 (PortP P23-15) --> USER_LED_1 (P7-1) * ETPUC9 (PortV P30-8) --> USER_SWITCHES (P6-4) ********************************************************************************

******************************************************************************** * File: main.c * Owner: b21190(Vlna Peter) * Version: 1.6 * Date: Oct-10-2017 * Classification: General Business Information * Brief: Example contains startup with PLL0 200MHz as system clock * and demonstrates PIT interrupt triggering. ******************************************************************************** * Test HW: MPC57xx EVB + MPC5746R minimodule * Maskset: 1N83M (cut 2.0B) * Target : internal_FLASH * Fsys: 200MHz PLL0 as system clock ******************************************************************************** Revision History: 1.0 Oct-19-2015 b21190(Vlna Peter) Initial Version 1.1 Nov-11-2015 b21190(Vlna Peter) Added PPL0 200MHz as system clock 1.2 Dec-02-2015 b21190(Vlna Peter) Added Flash controller init 1.3 Dec-02-2015 b21190(Vlna Peter) Fixed system clock init 1.4 Feb-07-2017 b21190(Vlna Peter) SWT0 and SWT1 disabled in startup 1.5 May-31-2017 b21190(Vlna Peter) Fixed comments in AC6 (CLKOUT) 1.6 Oct-10-2017 b21190(Vlna Peter) Added PIT + Interrupts *******************************************************************************/

******************************************************************************** * Detailed Description: * In case user want GHS to initialize all cores it is necessary to define * preprocessor symbol: init_cores * However in this example the cores are initialized from function: Core_Boot(); * This example demonstrates how to initialize clock module and activate core0, core1 and core0 locksteped core. * ------------------------------------------------------------------------------ * Test HW: MPC57xx EVB * Maskset: 0N78H * Target : internal_FLASH * Fsys: 200 MHz PLL * ******************************************************************************** Revision History: 1.0 Feb-08-2016 b21190(Vlna Peter) Initial Version 1.1 Feb-09-2016 b21190(Vlna Peter) Added Core_Boot() function *******************************************************************************/

This example follows application notes AN3283 and AN4365. It is intended for users who develop own JTAG programmer. It shows how to implement basic functions: - enter debug mode during reset - enable external debug mode - OnCE access to GPR, SPR and memory - Nexus access to memory The example is written in PRACTICE script language using Trace32 debugger from Lauterbach (www.lauterbach.com). Low level functions for JTAG are used, so users can see sequences of ‘0’s and ‘1’s which are sent to JTAG interface. Used commands are described in this document: www2.lauterbach.com/pdf/general_ref_j.pdf This example was tested on MPC5607B device and VLE instruction set was used for OnCE access.

This example shows I2C communication with NXP PCA24S08 memory. The simple MPC5xxx I2C driver is used, see driver code/description on https://community.freescale.com/docs/DOC-330972. EVB connection: P1.11 - A[10] .. I2C0 SDA P1.12 - A[11] .. I2C0 SCL ------------------------------------------------------------------------------ Test HW: TRK-MPC5606B Maskset: 0N13E Target : RAM, Flash Terminal: 115200, 8N1 Fsys: 64 MHz PLL with 8 MHz crystal reference in RUN0. PC terminal displays this info ... You can see following I2C bus signals for particular conditions … Writing byte “H” into address 0x28 Read content of the address 0x28 Writing string “Hello world!” into address 0x152 Reading page (16 bytes) from memory address 0x150

******************************************************************************** * Detailed Description: * * ECSM Error Generation Register EEGR is used to generate a non-correctable * or single bit ECC error in RAM. The bad data is accessed then, so the IVOR1 * exception is generated and handled. * This file shows also ECSM_combined_isr and how to correct the wrong data. * Use macro Induce_ECC_error_by_DMA_read to select whether ECC error will be * injected by DMA read or CPU read. * At the end of main file you can choose if single bit or multi bit is injected * and select particular ME/EE setup by comment/uncomment of particular function * calls. * * ------------------------------------------------------------------------------ * Test HW: XPC567XKIT516 - MPC5674ADAT516 Rev.C, MPC567XEVBFXMB Rev.B * MCU: PPC5674FMVYA264 * Terminal: 19200-8-no parity-1 stop bit-no flow control on eSCI_A * Fsys: 264/200/150/60 MHz * ********************************************************************************

******************************************************************************** * Detailed Description: * Purpose of the example is to show how to generate Multi bit ECC error in * internal SRAM or FLASH (user must choose it in the option at the end of main * function) and how to handle this error with respect to constraints given by * MPC5643L architecture (ECSM/RGM/FCCU relation and ECC error handling through * reset). The example is only possible to run in internal_FLASH target. Power- * -on-reset is required after downloading the code into MCU's flash. The example * displays notices in the terminal window (setting specified below). No other * external connection is required. * ------------------------------------------------------------------------------ * Test HW: xPC564xLKIT, PPC5643L Cut3 silicon * Target : internal_FLASH * Fsys: 120 MHz PLL0 * Debugger: Lauterbach Trace32 * PeMicro USB-ML-PPCNEXUS * Terminal: 19200-8-no parity-1 stop bit-no flow control via LINFlex0 * EVB connection: default * ********************************************************************************

******************************************************************************** * Detailed Description: * ADC end of conversion event is triggering DMA transfer which automatically * moves ADC measurement results of ADC_1 channel_0 into buffer ADC_reseult. * ------------------------------------------------------------------------------ * Test HW: MPC57xx * Maskset: 1N65H * Target : internal_FLASH * Fsys: 200 MHz PLL with 40 MHz crystal reference * ******************************************************************************** Revision History: 1.0 Mar-11-2015 b21190(Vlna Peter) Initial Version 1.1 Feb-21-2017 b21190(Vlna Peter) ADC triggering DMA *******************************************************************************/

******************************************************************************** * Detailed Description: * Application performs basic initialization, setup PLL to maximum allowed freq., * initializes interrupts, blinking one LED by interrupt, second LED by software * loop, initializes and display notice via UART terminal and then terminal ECHO. * The example configures the device for maximum performance (OPTIMIZATIONS_ON). * For XPC567XKIT516 it initializes EBI for mounted external SRAM device. * * ------------------------------------------------------------------------------ * Test HW: XPC567XKIT516 - MPC5674ADAT516 Rev.C, MPC567XEVBFXMB Rev.B * MCU: PPC5674FMVYA264 * Terminal: 19200-8-no parity-1 stop bit-no flow control on eSCI_A * Fsys: 264/200/150/60 MHz * Debugger: Lauterbach Trace32 * PeMicro USB-ML-PPCNEXUS * Target: RAM, internal_FLASH * EVB connection: ETPUC0(J24-0) -> USER_LED_8 (J5-8) * ETPUC1(J24-1) -> USER_LED_7 (J5-7)(to see blinking LEDs) * ********************************************************************************