Document describes possible reasons of result swap in eQADC's result FIFO and how to avoid it. Very preliminary version!

******************************************************************************** * Detailed Description: * This example content a driver for CGM module configuration. * ------------------------------------------------------------------------------ * Test HW:  MPC57xx Motherboard + MPC5744PE257DC minimodule, MPC5744P, * silicon mask set 1N65H * Target :  internal_FLASH* ********************************************************************************

Detailed Description:                      This config tool simplifies DCF records calculation for MPC5746C device.                 Look at HowToUse sheet for simple guideline, then work with DCF sheet                 Notes: - Macros have to be enabled!         BR, Petr

******************************************************************************** * Detailed Description: * Purpose of the example is to show how to generate EDC after ECC error in * internal FLASH. Error response in achieved by reading of pre-defined patterns * in UTEST area at address 0x00400080 which generates IVOR1 exception and FCCU * interrupt (FCCU_Alarm_Interrupt). * Example does not show any handling as it is application specific. * The example displays notices in the terminal window (connector J19 on * MPC57xx_Motherboard)(19200-8-no parity-1 stop bit-no flow control on eSCI_A). * No other external connection is required. * ------------------------------------------------------------------------------ * Test HW:         MPC57xx_Motherboard + MPC5744P-144DC * MCU:             PPC5744PFMLQ8,0N15P,QQAA1515N, Rev2.1B * Fsys:            200 MHz PLL with 40 MHz crystal reference * Debugger:        Lauterbach Trace32 * Target:          internal_FLASH, RAM * Terminal:        19200-8-no parity-1 stop bit-no flow control * EVB connection:  default ********************************************************************************

******************************************************************************** * Detailed Description: * Example configures Sigma_Delta ADC and periodically converts ANA0_SDA0 input * (EVB's potentiometer can be connected i.e. J53-1 --> PO15) and displays * results in the terminal window (USBtoUART bridge J21). Terminal settings is * 19200-8-no parity-1 stop bit-no flow control on eSCI_A. * * ------------------------------------------------------------------------------ * Test HW:         MPC5777C-512DS Rev.A + MPC57xx MOTHER BOARD Rev.C * MCU:             PPC5777CMM03 2N45H CTZZS1521A * Fsys:            PLL1 = core_clk = 264MHz, PLL0 = 192MHz * Debugger:        Lauterbach Trace32 * Target:          internal_FLASH * Terminal:        19200-8-no parity-1 stop bit-no flow control on eSCI_A *                  eSCI_A is USBtoUART bridge (connector J21) * EVB connection:  For ADC: J53-1 (EVB pot's wiper) --> PO15 (header P22) * ********************************************************************************

******************************************************************************** * Detailed Description: * This example shows how to reprogram the shadow flash. * * It is highly recommended to read application note "Preventing Device Lockout * via Censorship on MPC55xx and MPC563x Families" * http://www.freescale.com/files/32bit/doc/app_note/AN3787.pdf * * This examples erases the shadow flash, then it restores censorship information * and then NVUSRO nonvolatile register is reprogrammed to disable the watchdog. * The watchdog is disabled by clearing of bit WATCHDOG_EN in NVUSRO. It ensures * that watchdog is disabled automatically during startup of MCU. * Watchdog can be also disabled by software (shown in the code). * * It is important to execute the code from RAM memory because Read-While-Write * is not supported here. * * ------------------------------------------------------------------------------ * Test HW:  XPC56xxMB2 + XPC560B 144LQFP, SPC5604B, silicon mask set 2M27V * Target :  internal_FLASH, RAM * ********************************************************************************

******************************************************************************** * Detailed Description: * * Application initializes SPI0 module as a master and SPI2 module as a slave. * Data are sent from master to slave and from slave to master. After data are * received, interrupt for each module is handled and data are saved to global * variables. * * * ------------------------------------------------------------------------------ * Test HW:         MPC5775K-356DS, MPC57xx Motherboard * MCU:             PPC5775KMMY3A 0N76P * Fsys:            PLL0 266MHz *                    Z4 Core 133MHz * Debugger:        Lauterbach Trace32 *                  PeMicro USB-ML-PPCNEXUS * Target:          internal_FLASH (debug mode, release mode) * EVB connection:  P18.0 to P18.5 (CS_0) *                    P18.2 to P18.7 (SCK) *                    P18.3 to P18.9 (SIN - SOUT) *                    P18.4 to P18.8 (SOUT - SIN) * * ********************************************************************************

******************************************************************************** * Detailed Description: * DRUN mode with max core frequency(200MHz) generated from PPL0 * This example demonstrates ECC error injection to peripheral RAM *  and ECC error reporting to MEMU * --------------------------------------------------------------------------------------------- * Test HW:  MPC57xx * Maskset:  1N15P * Target :  internal_FLASH * Fsys:     200 MHz PLL with 40 MHz crystal reference *           ******************************************************************************** Revision History: 1.0     Apr-04-2016     b21190(Vlna Peter)  Initial Version 1.1    Aug-15-2017     b21190(Vlna Peter)  EIM ECC RAM error injection to DMA added *******************************************************************************/

******************************************************************************** * Detailed Description: * Application performs basic initialization, setup PLL to maximum allowed freq., * initializes interrupts, blinking one LED by interrupt, * initializes and display notice via UART terminal and then terminal ECHO. * ------------------------------------------------------------------------------ * Test HW:        XPC5607B 176LQFP, XPC56XX EVB MOTHEBOARD Rev.C * MCU:             PPC5607BMLUAM03Y * Fsys:             64/48 MHz * Debugger:      Lauterbach Trace32 *                      PeMicro USB-ML-PPCNEXUS * Target:           RAM, internal_FLASH * Terminal:       19200-8-no parity-1 stop bit-no flow control on LINFLEX_0 * EVB connection: default * ********************************************************************************

******************************************************************************** * Detailed Description: * * This example shows how to use CRC module. * - CRC32 is used * - byte stream is written into input register * - one test case uses direct access to CRC registers * - second test case uses DMA to write the data stream * - the results can be compared using this online calculator: *   http://www.zorc.breitbandkatze.de/crc.html * - screenshots from online calculator are attached * ------------------------------------------------------------------------------ * Test HW:         MPC574XG-324DS Rev.A + MPC574XG-MB Rev.C * MCU:             PPC5748GMMN6A 1N81M * Fsys:            160 MHz PLL * Debugger:        Lauterbach Trace32 * Target:          internal_FLASH ********************************************************************************

This is simple example of the usage of Flash Array Integrity Check (FAIC) function that is available on all MPC56xx devices.   The FAIC reads data from selected and unlocked flash blocks and calculates the MISR signature. User can compare the MISR signature calculated by flash controller (in runtime) with MISR calculated by offline tool (this is done during development, not in runtime) from s-record file. If the MISR is identical, we know that the content of selected flash blocks corresponds to content in s-record file and that there are no ECC errors (single bit or double bit ECC errors).

******************************************************************************** * Detailed Description: * Application performs basic initialization, setup PLL to maximum allowed freq., * initializes interrupts, blinking one LED by interrupt, second LED by software * loop, initializes and display notice via UART terminal and then terminal ECHO. * The example configures the device for maximum performance (OPTIMIZATIONS_ON) * by initialization of instruction cache and enabling of branch prediction. * Example suppose MCU is configured for LSM (Lock-step mode). * Its intention is to offer advanced startup code additional to CW stationery. * * ------------------------------------------------------------------------------ * Test HW:         xPC564xLKIT, PPC5643L Cut3 silicon * Target :         internal_FLASH, RAM * Fsys:            120 MHz PLL0 * Debugger:        Lauterbach Trace32 *                  PeMicro USB-ML-PPCNEXUS * Terminal:        19200-8-no parity-1 stop bit-no flow control via LINFlex0 * EVB connection:  default * ********************************************************************************

******************************************************************************** * Detailed Description: * Application performs basic initialization, setup PLL to maximum allowed freq., * initializes interrupts, blinking one LED by interrupt, second LED by software * loop, initializes and display notice via UART terminal and then terminal ECHO. * The example configures the device for maximum performance (OPTIMIZATIONS_ON). * For XPC564AKIT324S it initializes EBI for mounted external SRAM. * Its intention is to offer advanced startup code additional to CW stationery. * * ------------------------------------------------------------------------------ * Test HW:        XPC564AKIT208S and XPC564AKIT324S * MCU:            SPC5644AMMG1,0M14X and SPC5644AMVZ1,0M14X * Fsys:           150/132/120/12 MHz * Debugger:       Lauterbach Trace32 *                 PeMicro USB-ML-PPCNEXUS * Target:         RAM, internal_FLASH * Terminal:       19200-8-no parity-1 stop bit-no flow control on eSCI_A * EVB connection: default * ********************************************************************************

******************************************************************************** * Detailed Description: * Application performs basic initialization, setup PLL to maximum allowed freq., * initializes interrupts, blinking one LED by interrupt, third LED by software * loop, initializes and display notice via UART terminal and then terminal ECHO. * Second core is started and second LED blinking is being performed by it. * The example configures the device for maximum performance (OPTIMIZATIONS_ON) * by initialization of instruction cache and enabling of branch prediction. * Example suppose MCU is configured for DPM (Decoupled-parallel mode). * Its intention is to offer advanced startup code additional to CW stationery. * * ------------------------------------------------------------------------------ * Test HW:         xPC564xLKIT, PPC5643L Cut3 silicon * Target :         internal_FLASH, RAM * Fsys:            120 MHz PLL0 * Debugger:        Lauterbach Trace32 *                  PeMicro USB-ML-PPCNEXUS * Terminal:        19200-8-no parity-1 stop bit-no flow control via LINFlex0 * EVB connection:  default * ********************************************************************************

******************************************************************************** * Detailed Description: * Application performs basic initialization, setup PLL to maximum allowed freq., * initializes interrupts, blinking one LED by interrupt, second LED by software * loop, initializes and display notice via UART terminal and then terminal ECHO. * The example configures the device for maximum performance (OPTIMIZATIONS_ON). * IT INITIALIZES EBI FOR EXTERNAL SRAM CONNECTED TO XPC564AKIT324S AND TEST IT. * * ------------------------------------------------------------------------------ * Test HW:        XPC564AKIT324S * MCU:            SPC5644AMVZ1 0M14X QAK1235G * Fsys:           150/132/120/12 MHz * Debugger:       Lauterbach Trace32 * Target:         RAM, internal_FLASH * Terminal:       19200-8-no parity-1 stop bit-no flow control on eSCI_A * EVB connection: default * ********************************************************************************

Hello    If you want to do nothing on MCU, no-operation is used generally.     Additional mnemonics are provided for the preferred forms of no-op, like nop, e_nop, se_nop. (Where the semantics are similar but the binary encoding differ, the standard mnemonic is typically preceded with an e_ to denote a VLE instruction. To distinguish between similar instructions available in both 16- and 32-bit forms under VLE and standard instructions, VLE instructions encoded with 16 bits have an se_ prefix.)    When you compile these code within IDE, you can get the results as below. The code could run correctly except __asm__ ("nop").  Some MPC5xxx will stop at __asm__ ("nop").    "nop"         gives Book E NOP instruction which isn't valid on VLE only cores. "e_nop"     gives 32bit VLE instruction. "se_nop"   gives 16bit VLE instruction. Based on the summary within AN4802 (thanks for Randy Dee's working), Qorivva MPC57xx e200zx Core Differences, Book E is not supported by MPC57xx. VLE instruction set is supported only.   This is the reason that user should use "e_nop" or "se_nop" except "nop" on MPC57xx or S32R2xx. Cheers! Oliver

******************************************************************************** * Detailed Description: * Example show simple flash programming routine. During runtime it changes * content of field of constants 'test' (located in internal data flash). * Also it shows how to relocate data into FLASH (used linker command file * is MPC5675K_my_sections.lcf and MPC5675K_DEBUG_my_sections.lcf). * * Note: For complex tasks use SSD driver (Freescale site for particular device, * Software&Tools/Run-Time Software/Middleware-Device Drivers * ------------------------------------------------------------------------------ * Test HW:        MPC5675KEVB * MCU:            PPC5675KFMMSJ in Lock-Step mode * Fsys:           180/150 MHz CORE_CLK * Debugger:       Lauterbach Trace32 *                 PeMicro USB-ML-PPCNEXUS * Target:         RAM, internal_FLASH * Terminal:       19200-8-no parity-1 stop bit-no flow control on eSCI_A * EVB connection: default ********************************************************************************

******************************************************************************** * Detailed Description: * Application performs basic initialization then it initializes EBI for external * SRAM connected to MPC5777C-516DS and test it by write and read of block of * data. * * ------------------------------------------------------------------------------ * Test HW:         MPC5777C-512DS Rev.A + MPC57xx MOTHER BOARD Rev.C * MCU:             PPC5777CMM03 3N45H * Fsys:            PLL1 = core_clk = 264MHz, PLL0 = 192MHz * Debugger:        Lauterbach Trace32 * Target:          internal_FLASH * Terminal:        19200-8-no parity-1 stop bit-no flow control on eSCI_A * EVB connection:  jumper J4 on position 1-2 (choosing CS0) *                  EMIOS1 (PortI P16-0) --> USER_LED_1 (P7-1) to see LED blink ******************************************************************************** Revision History: Ver  Date         Author            Description of Changes 0.1  Jun-26-2017  David Tosenovjan  Initial version 0.2  Oct-13-2017  David Tosenovjan  Lower CLKOUT frequency 0.3  Feb-02-2020  David Tosenovjan  Corrected External_SRAM_MMU_init                                     Ported to S32 design studio *******************************************************************************/

******************************************************************************** * Detailed Description: * Application performs basic initialization, initializes interrupts and NMI for * WKPCFG pin (GPIO213). * User needs to connect ETPUC9 pin to user switch and general purpose output * ETPUA30 to user LED 1: * ETPUA30 (PortP P23-15) --> USER_LED_1 (P7-1) * WKPCFG  (PortC P10-4)  --> USER_SWITCHES (P6-4) * Jumper J523 position 1-2 needs to be OPEN! * * If rising edge is detected (i.e. button is pressed), machine check exception * is triggered and LED1 on is toggled. * * ------------------------------------------------------------------------------ * Test HW:         MPC5777C-512DS Rev.A + MPC57xx MOTHER BOARD Rev.C * MCU:             PPC5777CMM03 2N45H CTZZS1521A * Fsys:            PLL1 = core_clk = 264MHz, PLL0 = 192MHz * Debugger:        Lauterbach Trace32 * Target:          internal_FLASH * Terminal:        19200-8-no parity-1 stop bit-no flow control on eSCI_A * EVB connection:  ETPUA30 (PortP P23-15) --> USER_LED_1 (P7-1) *                  WKPCFG  (PortC P10-4)  --> USER_SWITCHES (P6-4) *                  Jumper J523 position 1-2 needs to be OPEN! ******************************************************************************** Revision History: Ver  Date         Author            Description of Changes 0.0  May-22-2019  David Tosenovjan  Initial version                            *******************************************************************************/

******************************************************************************** * Detailed Description: * * Configures the FlexCAN to transmit and receive a CAN message. * ECC reporting in the FlexCAN module is disabled. * * In this config, CAN_A transmits a message. CAN_B receives the message. * CAN_A MB8 is configured to send data. CAN_A sends message each 1sec. * This interval is generated by PIT. * CAN_B MB9 is configured to receive a message, SW polling is used. * * Connect CAN0-CANH on P15-1 to CAN1-CANH on P14-1 * Connect CAN0-CANL on P15-2 to CAN1-CANL on P14-2 * * * ------------------------------------------------------------------------------ * Test HW:         MPC5777C-512DS Rev.A + MPC57xx MOTHER BOARD Rev.C * MCU:             PPC5777CMM03 2N45H CTZZS1521A * Fsys:            PLL1 = core_clk = 264MHz, PLL0 = 192MHz * Debugger:        Lauterbach Trace32 * Target:          internal_FLASH * Terminal:        19200-8-no parity-1 stop bit-no flow control on eSCI_A *           use USB connector (J21) on minimodule * * EVB connection:  ETPUA30 (PortP P23-15) --> USER_LED_1 (P7-1) *                  ETPUA31 (PortP P23-14) --> USER_LED_2 (P7-2) * ********************************************************************************