Zephyr: Ramloader: RAM load not working on mimxrt1064-evk and zephyr4.1.

[mastergbc]

I followed the `Relocating to SDRAM` example with MIMXRT1064-EVK . I would like to ask about it. Because ram load did not work as expected.

1. I used MCUXpresso for vs code extension to get blinky sample from nxp_zephyr_nxp_v4_1_0 repository.

2. Added boards/mimxrt1064_evk.conf.

CONFIG_NXP_FLEXSPI_ROM_RAMLOADER=y​

3. Added boards/mimxrt1064_evk.overlay.

/ {
	chosen {
		zephyr,flash = &sdram_code;
		zephyr,sram = &sdram_data;
    };
};

&sdram0 {
        #address-cells = < 0x1 >;
        #size-cells = < 0x1 >;
        /* Divide SDRAM into two partitions for Code and Data */
        sdram_code: memory@0 {
                device_type = "memory";
                reg = <0x00000000 DT_SIZE_M(16)>;

        };
        sdram_data: memory@1000000 {
                device_type = "memory";
                reg = <0x01000000 DT_SIZE_M(16)>;
        };
};

4. build project. FLASH and RAM regions below:

Memory region         Used Size  Region Size  %age Used
           SDRAM:          0 GB        32 MB      0.00%
           FLASH:       32822 B        32 MB      0.10%
             RAM:        4288 B        16 MB      0.03%

5. build/zephyr/zephyr.map below:

<Text start region>
text            0x00000000000022c0     0x3648
                0x00000000000022c0                __text_region_start = .

<Text end region>
                0x0000000000005908                . = ALIGN (0x4)
                0x0000000000005908                __text_region_end = .

<Data start region>
datas           0x0000000001000000       0x1c load address 0x0000000080008000
                0x0000000001000000                __data_region_start = .
                0x0000000001000000                __data_start = .

<Data end region>
                0x0000000001000032                _net_buf_pool_list_end = .
                0x0000000001000032                __data_region_end = .

Why is the relocation for Ramload not working properly? Please let me know if I missed anything in following the guide.

[jacobwienecke · Accepted solution]

@mastergbc Can you try adding address translation for the child nodes?

I believe that the address translation was either performed automatically or the child nodes were indexing into the parent node in a previous version of zephyr.

&sdram0 {
	ranges = <0x00000000 0x80000000 DT_SIZE_M(32) >;
	#address-cells = < 0x1 >;
	#size-cells = < 0x1 >;
	/*Divide SDRAM into two partitions for Code and Data */
	sdram_code: memory@0 {
		device_type = "memory";
		reg = <0x00000000 DT_SIZE_M(16)>;
	};
	sdram_data: memory@1000000 {
		device_type = "memory";
		reg = <0x01000000 DT_SIZE_M(16)>;
	};
};

The ranges property will translate the base address in SDRAM to the CPU address. 

[mastergbc]

Good solution.

[Gavin_Jia]

Hi @mastergbc ,

Thanks for your interest in NXP MIMXRT series!

I followed the Chapter 3.3.2 and had the same issue. I am asking for expert help to confirm this issue, please wait for my news. Thanks!

Best regards,
Gavin