Issue with Configuring CAN FD Timing for Nominal 500 kbps and Data 2 Mbps on KW38 MCU

[rajparvez]

1. Description of the Issue: I am working with the NXP KW38 MCU and trying to configure CAN FD with the following parameters:

Nominal Baud Rate: 500 kbps
Data Baud Rate: 2 Mbps
Payload Size: 64 bytes
Peripheral Clock Frequency: 20 MHz
Nominal Sampling Point: 80%
Data Sampling Point: 70%

Despite following the SDK and reference manual guidelines, I encounter issues where the timing configuration results in either the FLEXCAN_SetFDBaudRate() API triggering assertions related to priDiv exceeding the allowable range or failing the communication itself.

2. Detailed Explanation of the Problem: I calculated the timing segments for both nominal and data phases and configured the preDivider, phaseSeg1, phaseSeg2, and propSeg according to the API's requirements. However, the function:
FLEXCAN_SetFDBaudRate(CAN_Type *base, uint32_t sourceClock_Hz, uint32_t baudRateFD_Bps, flexcan_timing_config_t timingConfig)
produces an assertion failure during configuration due to the following checks:

Assertion: priDiv <= sourceClock_Hz
Prescaler (priDiv) calculation leads to values exceeding 0xFF.

3. Configuration Code Snippet: Below is a summary of the configuration code I am using:
flexcan_config_t flexcanConfig;
flexcan_timing_config_t timingConfig;

// Setting prescaler and timing segments
flexcanConfig.preDivider = 1; // Prescaler for nominal phase
timingConfig.phaseSeg1 = 12; // For nominal phase
timingConfig.phaseSeg2 = 3; // For nominal phase
timingConfig.propSeg = 1; // For nominal phase
timingConfig.rJumpwidth = 3; // For nominal phase

// Data phase configuration
flexcanConfig.dataRatePrescaler = 0; // Prescaler for data phase
flexcanConfig.timingConfigData.phaseSeg1 = 3; // For data phase
flexcanConfig.timingConfigData.phaseSeg2 = 2; // For data phase
flexcanConfig.timingConfigData.propSeg = 1; // For data phase
flexcanConfig.timingConfigData.rJumpwidth = 2; // For data phase
FLEXCAN_FDInit(EXAMPLE_CAN, &flexcanConfig, EXAMPLE_CAN_CLK_FREQ, BYTES_IN_MB, false);

4. Issues Encountered:
The priDiv calculated by the API for the data phase exceeds 0xFF, triggering the assertion and causing the configuration to fail.
The total time quanta for nominal and data phases may not align with the expected requirements due to adjustments added by the API (4 for nominal and 3 for data).

5. Steps Taken to Resolve the Issue:
Verified the peripheral clock frequency (CLOCK_GetFreq()).
Adjusted timing segments multiple times to ensure the correct total TQs.
Checked the calculation logic for quantum in the SDK to align with the API's handling of segment additions.

6. Request for Support:
I need assistance to confirm if the timing configurations used are valid for the KW38.
Suggest alternative timing segment values or approaches to meet the desired baud rates without triggering assertions and meeting my requirements. Verify if there are known limitations or additional considerations for CAN FD timing on the KW38 MCU.

[Ricardo_Zamora]

Hello,

Hope you are doing well. Could you please help this community post?

[KW36] FlexCAN Bit Timing Parameters Setup - NXP Community

Even it is for KW36, it also could help you with KW38.

Regards,

Ricardo